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I'm actually using a BTF50060-1TEA in my application, it work's well and I'm happy enough.

But I would like to modify my application making possible to parallelize outputs of BTF in order to manages an higher current.

I know the fact that switches are never really equal and, at the end, the two (or more) channels are different and especially in the OFF-state one of the group will be faster than the other. This one will has to regulate di energy itself.

So what I could do in order to avoid or, at least, limitate this dangerous situation ? External freewheeling diode ? Other advices ?

Alberto

Solved! Go to Solution.

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Hi,

Thank you for posting on the infineon community.

The following issues occur while using MOSFETs in parallel,

1) Current imbalance due to mismatch in device characteristics.

2) Parasitic oscillations

**Current Imbalance:**

During non-switching periods, a current is distributed to parallel MOSFETs in inverse proportion to their on-resistance. The MOSFET with the lowest on-resistance will carry the highest current. The positive temperature coefficient of on-resistance naturally tends to compensate for a current imbalance and equalize the currents through each MOSFET. It is therefore considered that parallel MOSFETs rarely suffer thermal breakdown in a steady state. The temperature coefficient for the voltage drop across a MOSFET body diode is not positive. Therefore, parallel MOSETs could have a large imbalance in the sharing of a steady-state current while their body diodes are in conduction. In reality, however, the temperature of a MOSFET rises as its body diode passes a current. As a result, its on-resistance increases, reducing the current it is conducting. For this reason, an imbalance in steady-state current rarely poses a problem.

Method to reduce this imbalance: During this current imbalance, the current concentrates on the MOSFET with the lowest Vth, it is important to use MOSFETs with the same or almost the same Vth when paralleling many MOSFETs.

**Parasitic oscillations:**

Surge voltage VSurge occurs across the drain and source terminals of a MOSFET during switching, mainly due to the di/dt during turn-off and stray inductances in the drain terminal and wire leads.

VSurge=Ld (stray inductances)×di/dt

The oscillating voltage caused by VSurge passes to the gate via the drain-gate capacitance Cgd of a

MOSFET, forming a resonant circuit with the stray inductance L of the gate wire. High-current, high-speed MOSFETs have a very small internal gate resistance. Without an external gate resistor, the resonant circuit would have a large Q factor (1/R・√L/C). If resonance occurs, the resonance circuit generates a large oscillating voltage across the gate and source terminals of the MOSFET, causing parasitic oscillation. Unless the transient switching currents of the parallel MOSFETs are well balanced during turn-off, a current is unevenly distributed to the MOSFET that turns off later. This current causes a large voltage surge (oscillation) across its drain and source terminals, which in turn passes to the gate, causing an oscillating voltage to occur across the gate and source terminals. An excessive oscillating voltage could result in a gate-source overvoltage breakdown, a false turn-on, or an oscillation breakdown. When the fastest MOSFET turns off, its drain voltage rises. The increase in the drain voltage passes to the gate terminal of the other MOSFET via the gate-drain capacitance Cgd, resulting in unintended behavior of the MOSFET, which leads to parasitic oscillation. In addition, parallel MOSFETs share a common low-impedance path, which is also susceptible to parasitic oscillation. These oscillation occurs regardless of a drain-source load, a freewheel diode, a power supply, a common gate resistor and a gate drive circuit.

Regards,

Abhilash P

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Hi,

Thank you for posting on the infineon community.

The following issues occur while using MOSFETs in parallel,

1) Current imbalance due to mismatch in device characteristics.

2) Parasitic oscillations

**Current Imbalance:**

During non-switching periods, a current is distributed to parallel MOSFETs in inverse proportion to their on-resistance. The MOSFET with the lowest on-resistance will carry the highest current. The positive temperature coefficient of on-resistance naturally tends to compensate for a current imbalance and equalize the currents through each MOSFET. It is therefore considered that parallel MOSFETs rarely suffer thermal breakdown in a steady state. The temperature coefficient for the voltage drop across a MOSFET body diode is not positive. Therefore, parallel MOSETs could have a large imbalance in the sharing of a steady-state current while their body diodes are in conduction. In reality, however, the temperature of a MOSFET rises as its body diode passes a current. As a result, its on-resistance increases, reducing the current it is conducting. For this reason, an imbalance in steady-state current rarely poses a problem.

Method to reduce this imbalance: During this current imbalance, the current concentrates on the MOSFET with the lowest Vth, it is important to use MOSFETs with the same or almost the same Vth when paralleling many MOSFETs.

**Parasitic oscillations:**

Surge voltage VSurge occurs across the drain and source terminals of a MOSFET during switching, mainly due to the di/dt during turn-off and stray inductances in the drain terminal and wire leads.

VSurge=Ld (stray inductances)×di/dt

The oscillating voltage caused by VSurge passes to the gate via the drain-gate capacitance Cgd of a

MOSFET, forming a resonant circuit with the stray inductance L of the gate wire. High-current, high-speed MOSFETs have a very small internal gate resistance. Without an external gate resistor, the resonant circuit would have a large Q factor (1/R・√L/C). If resonance occurs, the resonance circuit generates a large oscillating voltage across the gate and source terminals of the MOSFET, causing parasitic oscillation. Unless the transient switching currents of the parallel MOSFETs are well balanced during turn-off, a current is unevenly distributed to the MOSFET that turns off later. This current causes a large voltage surge (oscillation) across its drain and source terminals, which in turn passes to the gate, causing an oscillating voltage to occur across the gate and source terminals. An excessive oscillating voltage could result in a gate-source overvoltage breakdown, a false turn-on, or an oscillation breakdown. When the fastest MOSFET turns off, its drain voltage rises. The increase in the drain voltage passes to the gate terminal of the other MOSFET via the gate-drain capacitance Cgd, resulting in unintended behavior of the MOSFET, which leads to parasitic oscillation. In addition, parallel MOSFETs share a common low-impedance path, which is also susceptible to parasitic oscillation. These oscillation occurs regardless of a drain-source load, a freewheel diode, a power supply, a common gate resistor and a gate drive circuit.

Regards,

Abhilash P