Output source voltage at 9.3V when drain connected to 24V - TLE75602-ESD

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msivill
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Hi, I am testing a board that I made, using the schematic bellow.  Outputs 2 and 3 are not behaving as intended.  I have the drains of outputs 2 and 3 connected to 24V via a selector resistor (pins 7 & 18).  When I turn the output on via the SPI bus, I am getting 9.3V at the source of both outputs (pins 8 & 17), not the 23.7V I expect to see.  Can you please help me to understand why this is happening, and what I may do to fix the issue?

msivill_0-1669753245151.png

 

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Neo_Qin
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Hi @msivill ,

Sorry about the late reply as I need some internal assistance.

1)  We recommend 24V to power the Vs Pin, so a lowest VDS can been obtained according to your application.

Although 24V is within the extended operation range, all the functionalities are anyhow granted. Small variation on some parameters (turn on and off times, current consumptions, etc.) could be expected.

Neo_Qin_0-1670232838969.png

2)  When the auto-configurable switches utilized in high-side configuration, the gates of the switches are supplied by a charge pump from Vs Pin. This means the Vdrain of specific channels cannot be higher than Vs, that's why a significant VDS voltage drop was observed previously.

 

Regards,

Neo

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Neo_Qin
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Hi, @msivill 

I noticed that there is a jumper between 24V and 5V, make sure it is disconnected.

If the problem persists, we will discuss it further.

Neo_Qin_0-1669771079839.png

 

Regards,

Neo

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msivill
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Lol no, there is no jumper between 24V and 5V.  This is just a schematic symbol for a selector resistor.  It is a place to put a 0 ohm resistor where the middle pad is shared, so only one resistor could be placed, either between 1 and 2 or 1 and 3.    The resistor between 1 and 3 is not populated. 

 

msivill_0-1669817702200.png

 

I have taken my measurements right at the pins on the IC, so I am certain that the drain is receiving 24V and the source is supplying 9.3V for both outputs.  

If I try to load the output any more than with the LED shown the voltage drops out entirely.  

Could my problem be because Vs is so much lower than the drain voltages?  Your spec sheet states that Vs is used to control the gate voltage, but it does not specify if there is a set relationship between the Vs voltage and the drain voltages of the outputs.  

msivill_1-1669818560882.png

 

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Neo_Qin
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Hi @msivill ,

Channels 2&3 may enter linear mode operation, so a significant VDS voltage drop (24V-9.3V=14.7V) is observed. Since the voltage level of VDD&IDLE/INx are not provided, as well as the OUT.OUTn & HWCR.ACT bits state, I cannot assert the reasons for this behavior.

Here are some suggestions that I hope it will help you:

1. As you mentioned earlier, make sure the correct supply voltage range for normal operation: 7V~18V for Vs, 3V~5.5V for VDD.

2. By properly configuring the IDLE (set to low) &INx (one of the input pins set to high), you can easily test the performance of channels 2&3 in Limp Home mode. More details please refer to the chapter 5 of the datasheet.

3. The SPI of TLE75602-ESD provides diagnosis information about the device and the load status, confirm that no undervoltage and overload occur in your application.

If you have any concerns, kindly let me know.

Regards, 

Neo

Thank you for your help.  I tried what you suggested and ran 24V to Vs and the outputs worked as expected.   Is this alright?  You said 7V ~18V, but I only have 24V, 5V, and 3.3V on my board.  

Is this a known issue?  I ask because the data sheet that I am referencing does not mention linear mode or show that there is a relationship between Vs and the maximum allowed drain voltage on the output.   The text in the overview makes it sound like it would operate just fine at 5V. 

msivill_0-1669995456051.png

 

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Neo_Qin
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5 likes given 250 replies posted 250 sign-ins

Hi @msivill ,

Sorry about the late reply as I need some internal assistance.

1)  We recommend 24V to power the Vs Pin, so a lowest VDS can been obtained according to your application.

Although 24V is within the extended operation range, all the functionalities are anyhow granted. Small variation on some parameters (turn on and off times, current consumptions, etc.) could be expected.

Neo_Qin_0-1670232838969.png

2)  When the auto-configurable switches utilized in high-side configuration, the gates of the switches are supplied by a charge pump from Vs Pin. This means the Vdrain of specific channels cannot be higher than Vs, that's why a significant VDS voltage drop was observed previously.

 

Regards,

Neo

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