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gunheelee
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Hi all,

I'm testing TLE9104SH. 

I want to make Channel 1~4 open(but now all channels are closed.).

Here is the question.

 

1. For this, I know that make EN pin(Hardware) high('1') , OUT_EN(in GLOBAL device status register) set('1') and IN(1~4) pin high('1'). is it correct?

 

2. To make the OUT_EN to high('1'), Like a image i have attached below, I sent 0x8780 through MOSI

and i receive 0xB726 thorough MISO, this means "Fault Communication", "Fault Global", "CWD_TO=1".

Why a Watchdog Error occurred?

gunheelee_1-1646877980540.png

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Vishnu_Nambrath
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Hello Gunheelee

The watchdog starts to work as soon as the device has finished start-up and all blocks are released from reset. Each correct SPI communication restarts the t_CWD timer.  If no valid communication is received within timeout, the t_CWD timer will expire and disable all outputs. In order to avoid this scenario,  please read or write some registers or control the output stages via SPI. Make sure each 50ms you should have some commands to TLE9104SH.

Regards 
Vishnu Nambrath

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Vishnu_Nambrath
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Hello, 
Can you please try a power-on reset and send "C781"?
The difference with your message is on the last bit. This change will result in parity bit change as well. 

Capture.PNG

Regards 
Vishnu Nambrath

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gunheelee
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Hi Vishnu,

Thank you for reply.

I have tested like you said to me.

There's some changes on OUTPUT1.

But OUTPUT1 does not last while INPUT1 is set.

Please see images i have attached below.

Some reason OUTPUT1 is clear after SPI done.

gunheelee_1-1646976642058.png

Regards

gunheelee

 

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Vishnu_Nambrath
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Hello Gunheelee, 

Please do a power-on reset via HW. (No need to send 8701) During this step, the register value will be set to 01.
Then send C781 to enable the output stage.

Please make sure IN1 pin is having high. By default the outputs are controlled by IN pins. 

After sometime, If you see the output is again going to high irrespective of IN1. Please capture the SI, SO and CLK at output low and output high events. 

Please also check it is happening for all channels.

One more hint, in  your image output low is for around 50ms and device watchdog timeout is also typically 50ms.

Regards 
Vishnu Nambrath

 

 

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gunheelee
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Thank you for reply.

I send 0xC10F(disable watchdog timeout) and then send 0xC781.

Now i can use a output!!!

There's one more question.

Why a Communication watchdog timeout occurred??

And when i use a TLE9104 like this(send 0xC10F, 0xC781 after system booting), is there any problem??

regard.

gunheelee

 

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Vishnu_Nambrath
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Hello Gunheelee, 

Depending on your application, you can disable or enable the communication watchdog. There are three reasons for the watchdog reset as given below.

  • No communication 
  • Wrong commands 
  • Frame not equals to 16 clocks

Can you please check the above issues are happening or not. Watchdog status can be monitored by CWD_TO register.
Please refer section 5.6 in datasheet for more details.

Regards 

Vishnu Nambrath

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gunheelee
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Thank you for reply.

In my case, I think watchdog timeout occurred as "No communication" maybe.

Because I can set/clear OUTPUT.

It means at least "Wrong command" and "Frame not equals to 16 clock" didn't occur.

What's "No communication" means?

 

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Vishnu_Nambrath
Moderator
Moderator 5 likes given 25 solutions authored 10 likes received
Moderator

Hello Gunheelee

The watchdog starts to work as soon as the device has finished start-up and all blocks are released from reset. Each correct SPI communication restarts the t_CWD timer.  If no valid communication is received within timeout, the t_CWD timer will expire and disable all outputs. In order to avoid this scenario,  please read or write some registers or control the output stages via SPI. Make sure each 50ms you should have some commands to TLE9104SH.

Regards 
Vishnu Nambrath

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gunheelee
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Thank you for reply.

 

So it need a 'ping' before every 50ms.

For now i don't need to use this, no problem with disable the watchdog.

Thank you.

Regards.

gunheelee

 

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