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Regarding the behavior of the IS pin at the time of failure described in the attached file,
could you tell us how the first small signal before IIS = IIS (FAULT) is output?
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Hello,
The small rise at the sense is because the sense current follows the output current. At the same time the VDS reduces and at some point reaches the VDS(OLOFF) threshold -> indicated via the sense. At another point later the VDS is too low and the sense signal decreases, until the load current reaches IL(OVL) and triggers the internal counter -> followed by IIS(FAULT) indication at the sense.
Best Regards,
Anshika
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Hello,
The small rise at the sense is because the sense current follows the output current. At the same time the VDS reduces and at some point reaches the VDS(OLOFF) threshold -> indicated via the sense. At another point later the VDS is too low and the sense signal decreases, until the load current reaches IL(OVL) and triggers the internal counter -> followed by IIS(FAULT) indication at the sense.
Best Regards,
Anshika
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Hello,
A little more explanation which might be helpful:
When VDS < VDS(OLOFF) the power output stage is switched ON and a current IIS(OLOFF) is provided by the sense pin. If the load is properly connected and there is no short circuit to battery, VDS ~ VS therefore VDS > VDS(OLOFF). In case of a short circuit to battery the voltage divider between VS – OUT – GND is unbalanced and VDS goes below the minimum VDS(OLOFF) and the sense is falling again.
It can appear as a little confusing as so many things happen in a very short time period and signals are rising and dropping very fast.
Best Regards,
Anshika