robustness of DS/VS in NVRAM

[Anonymous]

Is there any robustness or sustainability difference between DS and VS in NVRAM?

I found sometimes VS data is cleared when power corruption happens, but DS is not.

[BoonT_56]

maxsong created a very good article here which describes some of the intricacies of the nvram

WICED Smart BCM92073X EEPROM and SFLASH Layout

[MichaelF_56 · Accepted solution]

Note that VS and DS are just firmware representations.  Niether should change within the context of physical NVRAM/EEPROM.

However, the developers have seen cases where power corruption causes issues within EEPROM and may trigger a write (false logic level) when it is not intended.

HW write protect is enabled by default for this reason as the application has to toggle WP for a write to occur, potentially helping to avoid these types of anaolies.

Because serial flash (as opposed to EEPROM) leverages a much more involved process for writes, this is not an issue with serial flash.

j.t vik86