I2C Contention -> 2 Masters

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Anonymous
Not applicable

Hey Guys,

  We have developed a 9-Axis Sensor Fusion Demo using our upcoming Wireless Sensor Platform(WSP).  The Sensor Fusion is performed on a SiLabs EFM32 Cortex M3/M4F depending on the Starter Kit plugged into the WSP.  The EFM32 is configured as an I2C Master to communicate with the 9-Axis Motion Sensor.  The BCM2073xS which is also connected to the kit and we are using this to send the Sensor Fusion data to a PC and soon Mobile Apps is also connected to the Sensor board and also has the I2C lines running to the sensor although there is ZERO I2C firmware running on the BCM2073xS outside of the typical default Boot I2C scenario to the EEPROM.  Being that the internal EEPROM address is different than the Motion Sensor this should be fine.

  We have seen that when the BCM2073xS SDA/SCL lines are also tied into the Sensor(but should have zero effect) that there appears to be contention for some reason.  Upon starting code execution on the EFM32 the I2C comms is corrupted slightly to where the Motion Sensor does not initialize correctly?  We have clipped the SDA/SCL lines coming into the Sensor Board and everything works fine.  This contention is occurring after the BCM2073xS has been paried/bonded with a Client and there is no where else in the BCM firmware where NVRAM Read/Write functions are being used outside of when Host ID, Bonding info is stored so there should be no activity from the I2C module after BOOT and after pairing.

Question: 

1) If there is no I2C configuration on the BCM2076xS is it safe to operate with the I2C lines connected into a system with another I2C

      master in the system?  I can add a SCL/SDA disconnect switch but it seems unnecessary.

2) After the initial EEPROM boot upon a RESET/POR is there ANY I2C activity that occurs if the I2C module has not been configured

     outside of potential NVRAM Read/Writes?

Regards,

Frank

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1 Solution
Anonymous
Not applicable

Hey Frank,

1.  We don't support multi-Master I2C

2.  Any pairing, calling NVRAM, OTA Upgrade, etc, there will be activity on the I2C bus

Thanks

JT

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5 Replies
JacobT_81
Employee
Employee
250 replies posted 100 replies posted 50 replies posted

Hi Frank,

The biggest thing that sticks out to me is the pull up resistors. On the 20736S chips there are 10K pull up resistors external to the die. If you are pulling the line up on the other side, with a 4.7k, for instance, this may be detrimental to the timing of the I2C bus.

To my knowledge, there should be no activity on the i2c bus between nvram writes. I've had logic analyzers hooked up to a running app for hours without activity.


Do you get any successful reads/writes once the 20736S is connected (after init, to nvram, etc)?

Jacob

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jakewtorres


Note here that the I2C spec requires an external pull up on SCL and SDA.  The internal pullup is not sufficient because the part will not be configured until an I2C slave is detected (i.e. external pullup), which is a chicken-egg situation.


However, this only applies to the SoC. The pullups inside the SIP modules (shown on the internal schematic) are still external to the die, so the modules don't need pullups outside the module.

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Anonymous
Not applicable

Hey Frank,

1.  We don't support multi-Master I2C

2.  Any pairing, calling NVRAM, OTA Upgrade, etc, there will be activity on the I2C bus

Thanks

JT

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Anonymous
Not applicable

Hey Guys,

  Thanks for the response.  The issue happens upon POR when both sides a MCU and the BCM2073xS are initializing as we also initialize some sensors.  For this sensor platform I have added a switch to disconnect the BCM2073xS I2C from the Sensor Board I have developed if the MCU is the I2C Master.

Regards,

Frank

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Anonymous
Not applicable

Hey Frank,

Yes, the switch is a good idea.

JT

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