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Smart Bluetooth Forum Discussions

TeMa_1467596
Level 5
Level 5
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I'm creating a project that will use the new CYBT-343026 module which I understand is basically the same hardware as the CYW92070xV3_EVAL PCB.  I Have that eval PCB driving I2S to my SSM3582 digital amplifier eval board and it's working well.  I need to add a second I2S source which will be the TLV320ADC3101 from TI which converts an analog stereo audio signal to I2S that will be selectable as an alternate sound source - i.e. the BT streaming I2S or the I2S from the Aux input.

The TLV320ADC3101's I2S outputs can be tri-stated so I'm wondering if the same is true for the I2S output from the CYBT-343026 (which I think uses a CYW20706 Bluetooth SoC), if yes then I can simply connect the I2S signals in parallel and enable one or the other's output.  I'm not clear if/how I can make the I2S outputs go hi impedance using code.

Thanks in advance,

Ted

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JacobT_81
Employee
Employee
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On the 2070x platforms, the i2s lines should already be tristated any time a stream is not active. However, in an A2DP connection for instance, there is a delay between when the audio stops and the stream stop event is received. In this few second gap, the i2s lines will not be tristated, but there will also be no audio.

Jacob

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2 Replies
Anonymous
Not applicable

This function should help you out I think:

CyPins_SetPinDriveMode(SDO_1 ,PIN_DM_DIG_HIZ)

It will allow you to set the drive mode of a pin;

Not sure how it will interact with the I2S component however.

Pratt

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JacobT_81
Employee
Employee
250 likes received 100 likes received 50 likes received

On the 2070x platforms, the i2s lines should already be tristated any time a stream is not active. However, in an A2DP connection for instance, there is a delay between when the audio stops and the stream stop event is received. In this few second gap, the i2s lines will not be tristated, but there will also be no audio.

Jacob