Anonymous
Not applicable
Jul 31, 2013
02:57 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Jul 31, 2013
02:57 AM
Hi,
I want to know the number of the cycles till CQ/CQ# is stable.In the xilinx IP-Core it is given that 2048 cycles for the clock stable .
PART no :CY7C25632KV18.
Thanking you
Solved! Go to Solution.
Labels
- Labels:
-
SYNC
1 Solution
Anonymous
Not applicable
Aug 01, 2013
05:13 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 01, 2013
05:13 AM
Cypress follow the QDR consortium spec 20us for the clocks to become stable. However, QDRII+ 333MHz - 450MHz, SRAMs are ok with 2048 PLL lock cycles.
3 Replies
Anonymous
Not applicable
Aug 01, 2013
05:02 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 01, 2013
05:02 AM
Anonymous
Not applicable
Aug 01, 2013
05:13 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 01, 2013
05:13 AM
Cypress follow the QDR consortium spec 20us for the clocks to become stable. However, QDRII+ 333MHz - 450MHz, SRAMs are ok with 2048 PLL lock cycles.
Anonymous
Not applicable
Aug 02, 2013
04:47 AM
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Aug 02, 2013
04:47 AM
hi
Thanks