Mar 28, 2021
10:39 PM
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Mar 28, 2021
10:39 PM
I want to use QDRIV: CY7C4142KC13 as a memory for my Xilinx versal AI device.
The FAE of Xilinx said their hardware IP doesn't support QVLDA0,1&QVLDB0,1.
So could you tell me how should I connect QVLDA0,1&QVLDB0,1 rightly when these pins are not used?
Thanks very much.
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Memory SRAM
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Mar 29, 2021
04:10 AM
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Mar 29, 2021
04:10 AM
Hi,
The QVLD pins are output pins. You can leave them floating if you are not using them.
Thanks,
Pradipta.
2 Replies
Mar 29, 2021
04:10 AM
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Mar 29, 2021
04:10 AM
Hi,
The QVLD pins are output pins. You can leave them floating if you are not using them.
Thanks,
Pradipta.
Mar 29, 2021
06:59 PM
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Mar 29, 2021
06:59 PM
Hi, Pradipta
Thanks for the answer.