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SRAM

tatsu88liu
Level 1
First reply posted First question asked Welcome!
Level 1

I want to use QDRIV: CY7C4142KC13 as a memory for my Xilinx versal AI device.

The FAE of Xilinx said their hardware IP doesn't support QVLDA0,1&QVLDB0,1.

So could you tell me how should I connect QVLDA0,1&QVLDB0,1 rightly when these pins are not used?
Thanks very much.

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1 Solution
PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi,

The QVLD pins are output pins. You can leave them floating if you are not using them. 

Thanks,

Pradipta.

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2 Replies
PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi,

The QVLD pins are output pins. You can leave them floating if you are not using them. 

Thanks,

Pradipta.

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tatsu88liu
Level 1
First reply posted First question asked Welcome!
Level 1

Hi, Pradipta

Thanks for the answer.

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