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SRAM Forum Discussions

Anonymous
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Dear,

The datasheet of a pipelined SRAM (for example part CY7C1382KV33) states in the "Single Read Accesses" paragraph on page 8, that Consecutive read cycles are supported.  One single read cycle has a lantency of 2 Clk cycles.

Does this mean you can do a read cycle every 2 Clk cycles, or can you initiate a read cycle every Clk cycle?

Thanks and best regards,

Toma

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PradiptaB_11
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Hi Toma,

You can initiate a read cycle every Clk cycle if you want to perform back to back reads. You can also verify this in the datasheet on page 26, Figure 7, where we have shown one instance of consecutive reads.

Thanks and Regards,

Pradipta.

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PradiptaB_11
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500 replies posted 250 solutions authored 250 replies posted

Hi Toma,

You can initiate a read cycle every Clk cycle if you want to perform back to back reads. You can also verify this in the datasheet on page 26, Figure 7, where we have shown one instance of consecutive reads.

Thanks and Regards,

Pradipta.

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SudheeshK
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Hi Toma,

After the initial delay, you can read data at every clock cycle. Refer the timing diagram "Figure 7. Read/Write Cycle Timing" on page 26 of the datasheet (http://www.cypress.com/file/226446/download ). Please check how data from locations 'A1' and 'A2' are read out.

-Sudheesh

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