We are using the CY7C4122KV13/CY7C4142KV13 SRAM in our design, with the address parity logic enabled. For the same:
1) We need the switching characteristics and Switching Waveforms for Address Parity and Parity Error operations as they were not available in the product datasheet.
2) Also, I have a two part query I'll illustrated with an example. Suppose we initiated a transaction T0 and within the RL cycles of T0, we initiate two more transactions T1 and T2. After RL cycles, we receive a Parity Error for T0. Then:
a) if the parity error counter indicates there was only 1 error and after clearing the parity error, should all the transactions. i.e. T0, T1 and T2 need to be repeated or only the first transaction (T0).
b) related to this, if the parity error counter indicates there were 2 errors, does this imply that the first 2 consecutive transactions (T0 and T1) failed or can it be T0 and T2?
It would be ideal if a dedicated documentation for the address parity implementation is available.
I tried downloading the BSDL file for the following component part number: cy7c1512kv18-250bzi. I was inspecting the BSDL file (please see attached) and saw that there were two instructions with the same bit. Would it be okay to combine the two instructions into one? Is there an updated BSDL for this component? Any information would be helpful. Thank you.
part number CY7C4285V-15ASI, the pin 55 for this part is GND part, but it is open, it is not connect with the wafer. would this be an problem to use the part ? will this cause the reliability problem?Show Less
Working on a retro style CPU using mostly HC logic chips for fun.
I wanted to try something different with the register file.
I could build it too with 8 bit wide logic chips but thought I'd try using a small ram as the register file.
The cpu in question will work as follows.
On the low level of the clock the control lines will be setup
- a "read" address on the register file whose value will be fed into the ALU and also
- a "write" address on the register file where the ALU result will be written
On the rising edge of the clock the result of the ALU is latched into the slot identified by the write address.
The write address might be the same as the read address or a different location.
So in a single cycle data is fetched from the register file and looped back into the register file.
The general idea is as shown below. Though actually there are two "Read" addresses and one "write" address.
The thing below is build at the moment using a bunch of +ve edge triggered latches and a demultiplexer to select the "In" and "Out" instances.
To make the above work in a single clock cycle I need only the "In" data to be latched.
The Write/Read Addr and the "Out" are async (combinatorial) values.
I had considered putting a dual port SRAM in there instead of my edge triggered latches.
In this setup one of the ports would be always for "write" and the other port always for "read" (just like the sides of my existing 8 bit latches).
But a dual port async SRAM alone won't work as this potentially sets up a feedback loop from the "Out" back to the "In" via the ALU.
This feedback would happen whenever the WriteAddr and ReadAddr have the same value.
This feedback doesn't happen with my existing latches as the input to the latch only happens on the +ve edge.
Additionally there are these SRAM caveats in the docs about problems (busy and interrupts) when the Read and Write addresses are matching.
I noticed that dual port synchronous sram have this "flow through" feature and a latched input, which sounds promising.
However, these products also seem to have a latch on the output too.
And also latching on the addresses which will get in the way of the single cycle approach.
Does anyone have advice on these devices and concerns, and in particular whether this is even possible?
For Async SRAM, there are two timing parameters assosiated with read cycle, tDOE and tACE . tDOE is the maximum time from /OE Low to data valid and tACE is the maximum time from /CE Low to data valid on the bus during a read operation.
a) If you assert /CE at least (tACE - tDOE) time ahead of /OE , data will come at tDOE from the falling edge of /OE.
b) If you assert both /CE and /OE together, it will take tACE time from /CE or /OE falling edge for valid data to come on the bus.
Hope this clarifies the difference between the two parameters.
For your ASYNC SRAM, the datasheet doesn't identify address bit numbers (all address pins are identified as just "A"). what is the address bit number to package pin number mapping?
Since the ASYNC devices doesn't have an internal burst counter, the address numbering for Async SRAM's does not matter.
The pins can be connected in any way such that the routing is made simple.
The following link has the details-
The absolute maximum junction temperatue of Sync SRAM is 125 deg C and the junction temperature can be calculated from the following link: http://www.cypress.com/?docID=23984 .The calculated junction temperature should be less than 125 deg C.
We can also calculate the worst case junction temperature which can be calculated using the same tool under the worst case conditions. For example, consider the Sync SRAM CY7C2665KV18-550BZXC. The worst case Tj can be calculated by substituting the following values in the tool:
Vdd=1.9 (max), Idd =1520 mA (X36, Idd at max frequency), α=1, f=550 MHz, CL = 5pf (Tested load), Number of Switching IOs=36, Vddq=1.9(max), No of ODT inputs=42, R=50 Ohm, Ta=70 deg C, Theta Ja= 12.55 . This would give the value of Tj as 122.6 deg C. This can be considered as the worst case Tj and the recommended maximum value of Tj.
Cypress has introduced the newly designed spreadsheet to calculate the power consumption and junction temperature for Sync SRAM devices.
The following link will provide the options for both the HTML and Spreadsheet tools.
(1) Click this link to download the html file.
(2) Open the html file to get a webpage.
(3) Find the spreadsheet file for power calculation.
Some of Delta39K Family has Self-boot in one chip.
Is it possible to access data on flash memory from the implemented system. Is there any possibility to use data stored in flash memory implemented by the unit? I want use some part of integrated self-boot memory as "read only" memory.
How hard it can be?
Sorry for My English.
QDR (Quad Data Rate™) SRAMs are a family of SRAMs with separate Inputs and Outputs that each operate at Double Data Rates and are optimized for High Performance Networking Applications
In 1999, the QDR SRAM Co-Development Team was created to define a new family of SRAM architectures
for high-performance communications applications. Participating companies work closely together to ensure multiple sources for the new QDR SRAMs by developing pin- and function-compatible products. The QDR family of SRAM & products incorporates extensive input from networking industry leaders. QDR SRAM devices have two ports running independently at twice the rate of conventional synchronous memories, resulting in four data items per clock cycle. The QDR SRAM family of products includes Quad Data Rate and Double Data Rate common and separate I/O definitions. Depending on the application, products in the QDR SRAM family can more than double SRAM device efficiency per pin.
Click on the link below to access the QDR consortium website :