Assert CS (chip enable), and OE (output enable) pins Is it possible to continuously read the data signal by switching the address signal while keeping it? (Page lead)Show Less
I checked the data sheet, but it was not disclosed, so please let me check.
Are internal pull-up resistors installed on each of the control(CE1/OE/WE/BLE/BHE), address, and data pins?
Using the memory CY7C1380D-167AXI, I'm looking for some information about the SEU and MBU rates of the memory.
Newer parts datasheets have a “Neutron Soft Error Immunity” table included but this older part does not have that information included.
We've been using 62147 for years with no problems. Coupled with STM32F207IGH6. Our design allows for 62157 to be placed instead so we have A18 available and tie CE2 high. There is no other memory on the bus. With 62157 our memory test reports all kinds of different failures. In summary the kinds of effects are:
- adjacent words mostly get repeated when being read consecutively. Possible cross-talk between A0 and A1 but its not consistent as sometimes both words do get read correctly
- writes sometimes seem to fail. For instance if we pattern fill the memory and then zero fill, sometimes some of the locations retain their previously written values
- over time a zero filled memory space will gradually get corrupted with what seem like random values
I suspect that this is all due to some basic hardware issue or FSMC configuration that doesn't show with 62147 but the datasheets seem identical in all respects.
We are re-spinning a design that uses a CY62147EV30LL-45BVXI SRAM - Asynchronous Memory IC 4Mb (256K x 16) Parallel 45 ns 48-VFBGA (6x8). Wondering if there is a newer part to use? Looks like the CY62147G30-45BVXI is a drop-in. Also looks like the ERR pin version, CY62147GE30-45BVXI would also work.
What would you recommend to put as the primary part on the parts list. And what other parts can we list as drop-in substitutes.
I am using CY62167EV30LL, I want to share this memory between 2 microcontrollers.
Query 1: can we share it? If yes, please suggest the solution.
I have thought to share half address line between the two microcontroller.
Other way around to mux the address line between the two controller and separate data lines for each controller.
Please suggest the solution.
Hello, in this post "https://community.infineon.com/t5/SRAM/QDR-IV-memory-controller-for-Zynq-Ultrascale/m-p/266947" infineon says that there is a internal controller for a single device.
I would like to use a single QDR-IV device but Vivado doesen't provide interface for CY7C4121KV13 18 bits wide.
Is it possible for infineon to share our controller or provide a third part that will provide us?
I think there are synchronous and asynchronous SRAM of Cypress, but I would like to know the main lineup of synchronous SRAM such as serial and parallel products.Show Less
This SRAM :CY62167EV30LL-45BVI is used in our product and no longer available. I appreciate your help to find a replacement for it. Ideally a drop-in replacement and if not please advise on the options.