I believe there are errors in the datasheet for P/N CY7C1380D. Please check
the following issues:
1. The timing diagrams on pages 24 and on are visually corrupted. The hatching used
to indicated don't care is only partially visible which makes the diagram confusing.
2. The "Functional overview" section describes the various access patterns for using the device.
However, the descriptions don't match up with the waveforms (even disregarding the visual issues).
For example, the description of "Single Read Accesses" asserts that during the first cycle of an ADSP_N read, the write signals GW_n/BWE_n must be deasserted. But the diagram marks them as Don't Care.
I compared both the diagram and the description to a newer datasheet for P/N CY7C1381KV33
and neither problem appears there. I believe that in (2) above the datasheet verbal description is wrong (indeed, it does not match the one in CY7C1381KV33). And the corrupted diagram seems
to be identical to the one in the newer datasheet, except for the missing hatched lines.
I've been unable to contact support so I'm hoping they keep an eye on reports via this channel.
In the CY7C1380KV33 data sheet which Electrical and Switching parameters are tested at temperature and which are only tested at lab ambient? Are all components subjected to temperature testing or are only a sample per lot, date code... tested at temperature?Show Less
Good morning, I am currently working on the development of a product which includes CY62157EV30LL-45ZXA SRAM.
We are using the device in 8-bit data mode, using address pins A0-A19, with BHE and BLE tied high, and BYTE tied low.
In many areas of the datasheet, it is specified that '29. During this period, the I/Os are in output state. Do not apply input signals.'
We understand this that if the I/Os are in an output state, and we drive a voltage into these pins at this time - it is possible that we may physically damage the memory. We are not comfortable shipping a product that could be damaged by firmware - validated firmware or not.
Are we understanding this correctly? And in such a case, would Infineon recommend the use of series resistors on the data lines to stay within the 20mA 'output current into outputs (LOW)' specification, within the maximum ratings section of the datasheet?
Many thanks in advance
Hi ,in my board, i use Xilinx IP to Access CY7C2665KV18.
when in write process, BWS signal looks strange, maybe with ODT Problem.
The yellow signal is WPS signal
The green signal is BWS signal
When WPS is high, BWS signal can toggle around 750mV
But when WPS is Low, in write process, BWS signal can't higher than 750mV
I can't find in the data-sheet CY7C1168KV18 Vref current consumption.
In the application not it is recommended to add to Vref decoupling capacitors total of 12.3uF while in the TPS51200DRC (the LDO for VTT I'm using) the limit capacitance on vref is 0.47uF. Is 0.47uF is sufficient?
I'm currently working on CY7C1471BV33-133BZI SRAM. Interfaced with MPC5777C power architecture via EBI.
I'm using Chip select 0 for communication, I also attached the schematic for reference.
Here my problem I'm able write data in SRAM but not in a particular address , When I try to write in one address data being written in all address. Is there any configuration I need to do?
kindly please respond and help me out with this.Show Less
We are using the CY7C4122KV13/CY7C4142KV13 SRAM in our design, with the address parity logic enabled. For the same:
1) We need the switching characteristics and Switching Waveforms for Address Parity and Parity Error operations as they were not available in the product datasheet.
2) Also, I have a two part query I'll illustrated with an example. Suppose we initiated a transaction T0 and within the RL cycles of T0, we initiate two more transactions T1 and T2. After RL cycles, we receive a Parity Error for T0. Then:
a) if the parity error counter indicates there was only 1 error and after clearing the parity error, should all the transactions. i.e. T0, T1 and T2 need to be repeated or only the first transaction (T0).
b) related to this, if the parity error counter indicates there were 2 errors, does this imply that the first 2 consecutive transactions (T0 and T1) failed or can it be T0 and T2?
It would be ideal if a dedicated documentation for the address parity implementation is available.
GreenSoft Technology, a leading provider of environmental compliance data management services and software for the global electronics industry (http://www.greensofttech.com), has been contracted by Nortek to collect compliance data on parts purchased from your company.
Please note that Nortek might not purchase directly from your company but via a reseller or distributor. In addition, you may need to collect material or compliance documents from your suppliers to fulfill this request. Your support to Nortek is highly appreciated.
One of your parts that they are requesting data for is:
Description: IC, SRAM, 2MBIT, 128K X 16, 45NS, TSOP-44
Description: IC, SRAM, 8MBIT, 512K X 16, 45NS, FBGA-48 (6X8MM)
Description: IC, CY8C27443-PVXIT, MCU, 16KB, SSOP-28
Description: IC, CY8C29666-24PVXIT, MCU, 32KB, SSOP-48
Description: IC, FLASH, 8MBIT (1MB X 8 / 512K X 16), 70NS MAX, FBGA-48 (6X8MM)
Can you please provide the following environmental compliance data for this part:
- REACH Declaration or SVHC Certificate. If a product contains any SVHC or Substances of REACH - Annex XIV, please provide the substance name and concentration, as well as future plan to eliminate its use.
- If reportable SVHCs are identified, please provide the SCIP data (SCIP – per Waste Framework Directive 2008/98/EC, amended by Directive (EU) 2018/851)
- Full Material Disclosure (FMD), MSDS or similar document in your standard format if available
- CA Prop65 Certificate of Compliance (CoC); a template is attached.
Generally, the parts applicable for 6a/6b/6c RoHS alloy exemptions would form an article, such as a pin, connector shell, standoff, screw, or bracket. Therefore, Lead concentration of such parts is likely to exceed 1000ppm at Article level, which needs your further support to provide the SCIP information. However, if you confirm your products are SVHC compliant, please provide the Article Name.
If you cannot recognize a part or it’s incorrect, please indicate such in your feedback.
Please respond as soon as possible or provide an expected date of completion and we will follow up. We may contact you if any clarification is needed. Nortek is committed to providing its customers with products that meet the highest standards of innovation, performance and environmental safety and expects your timely response
If you have any questions, you can contact me at Cora@greensoft-china.com or call +1 323-254-5961 x813 (I am based in China; we also have someone in our US office that can answer your questions).
GreenSoft Technology, Inc.
155 S. El Molino Ave, Suite 100,
Pasadena, CA 91101, USA
GreenSoft Technology – China Office
No 368, North Xinshi Rd, FL12
I'm trying to get a datasheet of PSD813F2A-90J in the following site, but I couldn't find the correct datasheet there.
Hope you can help me as soon as possible.
Thanks in advance.Show Less
I tried downloading the BSDL file for the following component part number: cy7c1512kv18-250bzi. I was inspecting the BSDL file (please see attached) and saw that there were two instructions with the same bit. Would it be okay to combine the two instructions into one? Is there an updated BSDL for this component? Any information would be helpful. Thank you.