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SRAM Forum Discussions

MAO
SRAM
Assert CS (chip enable), and OE (output enable) pins Is it possible to continuously read the data signal by switching the address signal while keeping... Show More
jwilo
SRAM
Good morning, I am currently working on the development of a product which includes CY62157EV30LL-45ZXA SRAM. We are using the device in 8-bit data mo... Show More
HiKu_1337496
SRAM
Hi, I checked the data sheet, but it was not disclosed, so please let me check.Are internal pull-up resistors installed on each of the control(CE1/OE/... Show More
YangZhong
SRAM
Hi ,in my board, i use Xilinx IP to Access  CY7C2665KV18. when in write process, BWS signal looks strange, maybe with ODT Problem. The yellow signal ... Show More
JpW_810898
SRAM
Hi, Using the memory CY7C1380D-167AXI, I'm looking for some information about the SEU and MBU rates of the memory. Newer parts datasheets have a “Neut... Show More
tonytelemisis
SRAM
We've been using 62147 for years with no problems. Coupled with STM32F207IGH6. Our design allows for 62157 to be placed instead so we have A18 availab... Show More
mark63122
SRAM
Hello, We are re-spinning a design that uses a CY62147EV30LL-45BVXI SRAM - Asynchronous Memory IC 4Mb (256K x 16) Parallel 45 ns 48-VFBGA (6x8). Wonde... Show More
Harpreetsingh
SRAM
I am using CY62167EV30LL, I want to share this memory between 2 microcontrollers.  Query 1: can we share it? If yes, please suggest the solution. I ha... Show More
ErezN
SRAM
Hi, CY7C1168KV18 contain bidirectional data bus DQ. The DQ port has build in serial termination but lack of active pull-up termination (for receiving ... Show More
ErezN
SRAM
Hi, I can't find in the data-sheet CY7C1168KV18 Vref current consumption. In the application not it is recommended to add to Vref decoupling capacitor... Show More
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SRAM

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