SRAM Forum Discussions

Hello,

The QDR datasheet recommends that during power up sequence to apply Vdd before Vddq. Is it mandatory during the power up sequence to apply Vdd before Vddq?

thanks

alexsunny

I want to use QDRIV: CY7C4142KC13 as a memory for my Xilinx versal AI device.

The FAE of Xilinx said their hardware IP doesn't support QVLDA0,1&QVLDB0,1.

So could you tell me how should I connect QVLDA0,1&QVLDB0,1 rightly when these pins are not used?
Thanks very much.

Could you please provide the requested information for below parts?

When is Production start year?

Is this part is in production now?

Is this part is EOL ? please provide the LTB and LTS date.

Is this part supported min 7 years from now? if not please mention the No. of the years supported?

Is the current technology used in the part supported for NPI projects?

For CY7C1512KV18-300BZXC, is it comes in Tape and Reel packaging?
If yes, please let us know the Part in tape and Reel packaging and whether its available or not.

In one design we use the SRAM CY62167EV30LL-45BVXI with 65nm technology.

The data sheet CY62167EV30_MOBL_16_MBIT_1M_X_16_2M_X_8_STATIC_RAM.pdf says
"The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. "

A date is read from an address from the FLASH and this date is stored in the same address in the SRAM. Then the address will not be toggled.

Is it possible during this process that the SRAM goes into automatic power down?

How is the timing for the required address toggling defined?

The case would be very bad if the same address in the SRAM was written several times with different dates in succession. The SRAM is permanently chipselect with /CE1 and write is / WE controlled.
The last date is then not written because the SRAM has gone into power down due to the missing address toggling.
The SRAM can only be powered up again with a chip select /CE1=0 to 1 to 0.

Are 2 write commands possible in succession on this SRAM?

Hence my question about the time in ns at which the address must absolutely change so that the SRAM does not go into power down. This time is not in the data sheet. /CE1 is permanently low.

With best regards
Max Power

Hello!

We have been using the CP62167EV30LL-45BVXI memory on our modules since 2014.

We were affected by the AN66311 in 2014
"TIMING RECOMMENDATIONS FOR BYTE ENABLES AND CHIP ENABLES IN MOBL (R) SRAMS - AN66311"

After this bug was fixed by Cypress and we received new CP62167EV30 components, the error on our modules disappeared.

Until now in 2021.

Memory errors are now increasingly occurring on our assemblies during the final inspection, failure rate approx. 50%. After asking us, we were able to determine that Cypress has changed this SRAM from 90nm technology to 65nm technology.

Hello!

I looked at the data sheet and compared it with the old one and couldn't see any significant changes. An analysis of the memory accesses, timing, etc. on the defective assemblies has not been successful either.

If defective modules from production are equipped with the previous 90nm CP62167EV30LL-45BVXI, then they will function properly again.

Could it be that by changing the technology from 90nm to 65nm, the old bug from AN66311 was redesigned.

I am grateful for a quick answer.

greeting
Max power

Dear Team,

Kindly let me know which is the best recommended DPRAM for new design and what is the life cycle of the same.

Previously I had used CY7C025-15AI for my design which is obsolete now.

Kindly let me know at the earliest.

Regards

Krishna

Hi there,

My engineering asked me a question about the fab-site description of marking code, please advise:

P/N: CY62167EV30LL-45BVXI 

Where is the FAB SITE for code: F 04? in line 4

and where is for code: AB33?