SRAM Forum Discussions
(1) In the RAM ARRAY section, 1M x 16/2M x 8 is shown, and depending on the input status of the control signal, either of these configurations can be changed (contents of the Truth Table).
This is the same for CY62167EV30LL-45ZXIT under the same conditions, is this correct?
Is it correct that CY62167EV30LL-45ZXIT will have the same configuration under the same conditions?
(2) CY62167G30-45ZXIT has newly added ECC ENCODE and ECC DECODE on the block diagram, how much response delay does this cause?
Or is it correct to assume that the block DATAin DRAIVERS, RAM ARRAY, and SENSE ARMS, which are also in CY62167EV30LL-45ZXIT, have a different configuration than before, and the delay is offset by the faster response speed in these areas?
(3) Just to be sure, please let us know if there are any important access timing points when using CY62167G30-45ZXIT.
(5) Just to be sure, if there are any important points in access timing when using this RAM, please let us know. If you say that it is sufficient to satisfy the AC characteristics described, that is OK.
I heard that CE must be asserted after the address is determined due to operation restrictions by other manufacturers,
I had to put in an extra WAIT to compensate for the response delay of the ECC circuit, and so on.
This is a confirmation of the problem.
(4) The recommended operating voltage of the CY62167G30-45ZXIT is 4.5 to 5.5V, whereas the CY62167EV30LL-45ZXIT
Is it correct to assume that the specifications are the same as when the product is used at 4.5 to 5.5V?
Is it correct to assume that it is the same as when using 4.5 to 5.5V?
Block diagram of CY62167G30-45ZXIT
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Hi Team,
I am working on CY62157EV30LL 45ZXi SRAM chip on imx53 processor connected through EIM interface.
1.When I write data , it hsows as written proper data but when reading it shows same 2 byte data reading for other 2 bytes also.
Example, 0x12345678 is written , when read backs it shows as 0x12341234
2. When I read for next address and so on , it shows the previously read value only like 0x12341234 as shown below
debian@arm:~$ sudo ./devmem2 0xf0000000 w 0x12345678
/dev/mem opened.
Memory mapped at address 0xb6fed000.
Value at address 0xF0000000 (0xb6fed000): 0xABCDABCD
Written 0x12345678; readback 0x12341234
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$ sudo ./devmem2 0xf0000000
/dev/mem opened.
Memory mapped at address 0xb6ff0000.
Value at address 0xF0000000 (0xb6ff0000): 0x12341234
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$
debian@arm:~$ sudo ./devmem2 0xf0000004
/dev/mem opened.
Memory mapped at address 0xb6fde000.
Value at address 0xF0000004 (0xb6fde004): 0x12341234
debian@arm:~$ sudo ./devmem2 0xf0000008
/dev/mem opened.
Memory mapped at address 0xb6fbe000.
Value at address 0xF0000008 (0xb6fbe008): 0x12341234
3.Can anyine tell me what are the working timing parameters to be configured on imx side for cy6215 sram chip.
4.How to change the EIM frequency
Show LessAre there any time restrictions, etc. for BHE/BLE with respect to address signals?
For example, Liontech's SRAM LY62L409716A(https://protect2.fireeye.com/v1/url?k=31323334-501d0a38-31314cae-454441504e31-b458843b1000309f&q=1&e=e607cbae-0409-4a20-a0c6-d6eae17bbeb4&u=http%3A%2F%2Fwww.lyontek.com.tw%2Fpdf%2Flp%2FLY62L409716A-1.2.pdf%29%25E3%2581%25A7%25E3%2581%25AF%25E3%2580%2581
LB#, UB# (equivalent to BHE, BLE), etc. on P.6 Note.3
Show LessNeed a clarification for CY62157EV30LL-45ZSXI (Supposed to be 90nm Process Product ) received with Mark Die Revision AB33 which is from UMC Fab site 12A, could be of 65nm Process Product ?
If it is a 65nm Process, how come the Device Top Marking is CY62157EV30LL-45ZSXI?
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Please help to check the chip, may i know the whether the chip construction is correct
CY62157EV30LL-45ZSXIT DC 2237 Lot# 612226025 COO: Philippines
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HI i am searching for drop in replacement to SRAM CY7C185-15VC. Please help
Hello,
The customer is considering reducing the power consumption of equipment that is in standby mode for a long period of time.
The power supply to Sync SRAM cannot be stopped because it is shared with other devices.
Therefore, I'm thinking of stopping the clock signal from FPGA to SRAM to reduce power consumption.
1) What is the current consumption of SRAM in Standby: Clock stopped?
2) This SRAM has DOFF# (PLL turn off).
Is it possible to reduce power consumption by setting this pin to High as well?
What is the current consumption with Clock stopped and PLL turned off?
MPN: CY7C2265KV18-550BZXI
Best regards,
Naoaki Morimoto
Show LessHi,
Good day!!
Can you please provide the ESD Voltage rating of HBM for these below parts ? we can’t be able to find in the datasheet.
- IRFR120ZTRPBF
- FM16W08-SG
- CY14E116L-ZS25XI
- IRLML0100TRPBF
- CY7C199D-10VXIT
Site - Vermont, USA.
Thank you.
Show LessHi,
Do you know if 144Mb QDR-IV XP SRAM QDR CY7C4122KV13 supported by ARM Cortex A-72 and ARM Cortex R-5F? Thank you.
What are the standby mode supply voltage conditions for the above products?