SRAM Forum Discussions

Ultra Low Power SRAMs also called as More Battery Life (MoBL) have made their way into various applications-

mobile phones, PDAs, Point of Sale (POS) terminals and pacemakers etc. Most of the applications use a Battery 

and an SRAM to store critical data in case of power failure. The critical data is stored in the SRAM powered 

by a battery. Hence,low standby power is a critical requirement for the MoBL SRAM. Battery backed 

applications are used extensively due to low cost-simple-quick-to-market system solutions. Over the years due 

to the advantage of technology/device scaling, easy migration happened from 250nm to 90nm for MoBL SRAMs. For 

example 4M (Buswidth/Databits of 😎 MoBL Cypress SRAM in 250nm had speed of 70ns and ISB max of 20uA and the 

same 4M MoBL Cypress SRAM offered in 90nm has speed of 45ns and ISB max of 7uA under same conditions. Even 

before the device scaling happened, the need for faster data rates in these applications demanded more 

databits/Buswidth for MoBL SRAM. Thus,MoBL devices with Buswidth/Databits of 16 have emerged. And also over 

the years the need existed for large amount of critical data to be stored in these applications made to 

achieve huge memory (SRAM)arrays with the help of device scaling. Today in 90nm technology as high as 64M 

(Buswidth of x16) density is offered by Cypress. Now Cypress being the Market leader for these MoBL SRAMs; is 

truly committed to Customers in offering Best-In-Class MoBL SRAM devices and is constantly thriving hard to 

improve the specs for these MoBL SRAMs

Hi,

I would like feedback from Point-Of-Sale (POS) System Designers on whether a "tamper-proof" feature built into our Low Power SRAMs that are used in POS terminals would be an interesting one? Curently, system-level methods are used outside of the SRAM, such that the contents of the memory are erased on detection of a tamper event. Just wondering if a built-in "self-erase" feature would be an interesting proposition.

Thanks,

-Anuj