SRAM Forum Discussions

Hi, the DDR2+ SRAM parts are supposed to have ODT on the DATA lines... but I don't see it in the ibis model.  I see it on the BWS and K/K* though.

Example from ddr2pb2l25_cy21xx.ibs (You can see where it says what the driving output impedance is, but the input impedance is unknown):

[Model Selector]    DATAIO
|
DATAIO50_TT_1.5   DATAIO models (50ohms) at TT conditions - 1.5V I/O
DATAIO50_FF_1.5   DATAIO models (50ohms) at FF conditions - 1.5V I/O
DATAIO50_TSF_1.5  DATAIO models (50ohms) at Typ Slow Fast conditions- 1.5V I/O
DATAIO30_TT_1.5   DATAIO models (30ohms) at TT conditions - 1.5V I/O
DATAIO30_FF_1.5   DATAIO models (30ohms) at FF conditions - 1.5V I/O
DATAIO30_TSF_1.5  DATAIO models (30ohms) at Typ Slow Fast conditions- 1.5V I/O
DATAIO40_TT_1.5   DATAIO models (40ohms) at TT conditions - 1.5V I/O
DATAIO40_FF_1.5   DATAIO models (40ohms) at FF conditions - 1.5V I/O
DATAIO40_TSF_1.5  DATAIO models (40ohms) at Typ Slow Fast conditions- 1.5V I/O
DATAIO60_TT_1.5   DATAIO models (60ohms) at TT conditions - 1.5V I/O
DATAIO60_FF_1.5   DATAIO models (60ohms) at FF conditions - 1.5V I/O
DATAIO60_TSF_1.5  DATAIO models (60ohms) at Typ Slow Fast conditions- 1.5V I/O
DATAIO70_TT_1.5   DATAIO models (70ohms) at TT conditions - 1.5V I/O
DATAIO70_FF_1.5   DATAIO models (70ohms) at FF conditions - 1.5V I/O

Thank you.

Does Cypress have any plan to include ECC in future memory products?

LVTTL is a JEDEC standard that references the input signal to ground. The output switching range is 0.4 to 2.4V for 3.3V LVTTL and 0.4 to 2.2V for 2.5V LVTTL .

HSTL is a technology-independent interface standard for digital ICs that calibrates the input signal to a reference voltage rather than to ground. This calibration enables a smaller I/O swing and improves performance. HSTL was developed for voltage-scalable and technology-independent I/O structures. The nominal logic-switching range is 0.65 to 0.85V for 1.5V HSTL, resulting in faster outputs with reduced power-dissipation and signal-integrity issues.

For more details refer to the article below:

http://www.edn.com/article/476349-Exploring_memory_interface_options.php

what do you recommend to tie the NC pins during power up?

can I float these pins if they are designated as NC?