SRAM Forum Discussions
Hello,
We are re-spinning a design that uses a CY62147EV30LL-45BVXI SRAM - Asynchronous Memory IC 4Mb (256K x 16) Parallel 45 ns 48-VFBGA (6x8). Wondering if there is a newer part to use? Looks like the CY62147G30-45BVXI is a drop-in. Also looks like the ERR pin version, CY62147GE30-45BVXI would also work.
What would you recommend to put as the primary part on the parts list. And what other parts can we list as drop-in substitutes.
Thanks!
Mark
Show LessI am using CY62167EV30LL, I want to share this memory between 2 microcontrollers.
Query 1: can we share it? If yes, please suggest the solution.
I have thought to share half address line between the two microcontroller.
Other way around to mux the address line between the two controller and separate data lines for each controller.
Please suggest the solution.
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Hi,
CY7C1168KV18 contain bidirectional data bus DQ.
The DQ port has build in serial termination but lack of active pull-up termination (for receiving mode).
The FPGA I'm using contain both termination (serial and active pull-up termination).
The question is should I add external pull-up termination to the DQ bus?
(In AN4065 design example DQ doesn't have active pull-up termination)
Show LessHi,
I can't find in the data-sheet CY7C1168KV18 Vref current consumption.
In the application not it is recommended to add to Vref decoupling capacitors total of 12.3uF while in the TPS51200DRC (the LDO for VTT I'm using) the limit capacitance on vref is 0.47uF. Is 0.47uF is sufficient?
Thanks,
Erez
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Hello, in this post "https://community.infineon.com/t5/SRAM/QDR-IV-memory-controller-for-Zynq-Ultrascale/m-p/266947" infineon says that there is a internal controller for a single device.
I would like to use a single QDR-IV device but Vivado doesen't provide interface for CY7C4121KV13 18 bits wide.
Is it possible for infineon to share our controller or provide a third part that will provide us?
Regards
Simone
Show LessI think there are synchronous and asynchronous SRAM of Cypress, but I would like to know the main lineup of synchronous SRAM such as serial and parallel products.
Show LessHello Infineon,
I'm conducting academic research in methods of reliability analysis with help of the 1021 SRAM series from Cypress, and I have a few questions:
1) Which test board is recommended for such work that is affordable but can accomplish the task?
2) Is there software or pre-developed code that could aid in this effort?
3) Is there a reliability report available for this technology for registered customers?
Thank you very much for your time,
Paul
Show LessThis SRAM :CY62167EV30LL-45BVI is used in our product and no longer available. I appreciate your help to find a replacement for it. Ideally a drop-in replacement and if not please advise on the options.
Assert CS(chip enable) and OE (output enable) pins
Is it possible to continuously read the data signal by switching the address signal? (Page Lead)
Hi,
I'm currently working on CY7C1471BV33-133BZI SRAM. Interfaced with MPC5777C power architecture via EBI.
I'm using Chip select 0 for communication, I also attached the schematic for reference.
Here my problem I'm able write data in SRAM but not in a particular address , When I try to write in one address data being written in all address. Is there any configuration I need to do?
kindly please respond and help me out with this.
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