SRAM Forum Discussions
I am working on CY62157EV30LL 45ZXi SRAM chip on imx53 processor connected through EIM interface.
1.When I write data , it hsows as written proper data but when reading it shows same 2 byte data reading for other 2 bytes also.
Example, 0x12345678 is written , when read backs it shows as 0x12341234
2. When I read for next address and so on , it shows the previously read value only like 0x12341234 as shown below
debian@arm:~$ sudo ./devmem2 0xf0000000 w 0x12345678
Memory mapped at address 0xb6fed000.
Value at address 0xF0000000 (0xb6fed000): 0xABCDABCD
Written 0x12345678; readback 0x12341234
debian@arm:~$ sudo ./devmem2 0xf0000000
Memory mapped at address 0xb6ff0000.
Value at address 0xF0000000 (0xb6ff0000): 0x12341234
debian@arm:~$ sudo ./devmem2 0xf0000004
Memory mapped at address 0xb6fde000.
Value at address 0xF0000004 (0xb6fde004): 0x12341234
debian@arm:~$ sudo ./devmem2 0xf0000008
Memory mapped at address 0xb6fbe000.
Value at address 0xF0000008 (0xb6fbe008): 0x12341234
3.Can anyine tell me what are the working timing parameters to be configured on imx side for cy6215 sram chip.
4.How to change the EIM frequencyShow Less
Are there any time restrictions, etc. for BHE/BLE with respect to address signals?
For example, Liontech's SRAM LY62L409716A(https://protect2.fireeye.com/v1/url?k=31323334-501d0a38-31314cae-454441504e31-b458843b1000309f&q=1&e=e607cbae-0409-4a20-a0c6-d6eae17bbeb4&u=http%3A%2F%2Fwww.lyontek.com.tw%2Fpdf%2Flp%2FLY62L409716A-1.2.pdf%29%25E3%2581%25A7%25E3%2581%25AF%25E3%2580%2581
LB#, UB# (equivalent to BHE, BLE), etc. on P.6 Note.3Show Less
Need a clarification for CY62157EV30LL-45ZSXI (Supposed to be 90nm Process Product ) received with Mark Die Revision AB33 which is from UMC Fab site 12A, could be of 65nm Process Product ?
If it is a 65nm Process, how come the Device Top Marking is CY62157EV30LL-45ZSXI?
Please help to check the chip, may i know the whether the chip construction is correct
CY62157EV30LL-45ZSXIT DC 2237 Lot# 612226025 COO: Philippines
The customer is considering reducing the power consumption of equipment that is in standby mode for a long period of time.
The power supply to Sync SRAM cannot be stopped because it is shared with other devices.
Therefore, I'm thinking of stopping the clock signal from FPGA to SRAM to reduce power consumption.
1) What is the current consumption of SRAM in Standby: Clock stopped?
2) This SRAM has DOFF# (PLL turn off).
Is it possible to reduce power consumption by setting this pin to High as well?
What is the current consumption with Clock stopped and PLL turned off?
Naoaki MorimotoShow Less
Can you please provide the ESD Voltage rating of HBM for these below parts ? we can’t be able to find in the datasheet.
Site - Vermont, USA.
Thank you.Show Less