SRAM Forum Discussions

Hi,

I used CY7C1339G-133AXC in the circuit, but it is obsolete now, do you have a replacement for it , which is Pin to Pin and has the same frequency ?

Thank you.

Hi,

My project requires to interface a DDR II+ SRAM with an Altera Arria10 device acting as a buffer memory. Arria10 datasheet states that it supports QDR SRAM IP only but QDR SRAM is out of my consideration due to my application do not require to write and read at the same time and furthermore I am out of IOs.

Seems like I have to create my own IP. Is anyone successfully doing this?

Thanks.

Regards,

Soo Cheng

Hi all,

How calculation Power requirement both static and dynamic for a DP SRAM

CY7C028V

Regards,

Phaniendra Kundeti

Dear,

The datasheet of a pipelined SRAM (for example part CY7C1382KV33) states in the "Single Read Accesses" paragraph on page 8, that Consecutive read cycles are supported.  One single read cycle has a lantency of 2 Clk cycles.

Does this mean you can do a read cycle every 2 Clk cycles, or can you initiate a read cycle every Clk cycle?

Thanks and best regards,

Toma

We are using STK12C68-5C55M @ high temperatures 150 deg C. I need relation between access times and temperature. What is teh max deviation @150 deg C. I could not find Temperature vs access time graph anywhere in cypress website/ datasheet.

We are Using CY62157V . we need Configruation setting for LPC4088 Controller.we are using folliwing configruation setting which corruts data in SRAM.:

typedef struct {

uint8_t ChipSelect; /*!< Chip select */

uint32_t Config; /*!< Configuration value */

int32_t WaitWen; /*!< Write Enable Wait */

int32_t WaitOen; /*!< Output Enable Wait */

int32_t WaitRd; /*!< Read Wait */

int32_t WaitPage; /*!< Page Access Wait */

int32_t WaitWr; /*!< Write Wait */

int32_t WaitTurn; /*!< Turn around wait */

} IP_EMC_STATIC_CONFIG_T;

STATIC const IP_EMC_STATIC_CONFIG_T CY62157EV30_config = {

1,

EMC_STATIC_CONFIG_MEM_WIDTH_16 |

EMC_STATIC_CONFIG_CS_POL_ACTIVE_LOW |

EMC_STATIC_CONFIG_BLS_HIGH /* |

EMC_CONFIG_BUFFER_ENABLE*/,

EMC_NANOSECOND(0),

EMC_NANOSECOND(35),

EMC_NANOSECOND(70),

EMC_NANOSECOND(70),

EMC_NANOSECOND(45),

EMC_CLOCK(4)

};

please send perfect Configuation setting.