SRAM Forum Discussions
I am new to this forum and I am a developer who is self-taught.
Recently I have some problem with some MCU boards interfacing with CY7C1061GE (1M x 16 bit, TSOP Async SRAM). In my memory test program, it was found that a single bit in ALL the other non-targeted words are toggled together the same bit of the targeted word (to the same sense). I could not think of a possibility/combination that how can it be caused by external wiring problem. Visual checks on the pins did not show any obvious soldering fault too.
Please enlighten me on any pin-fault that could cause this or if this is a problem on the Chip itself.
Thank you very much.
ST GohShow Less
QDRII+ Sram Q[17:0] and CQ outputs need ODT on the FPGA/ASIC side ? If yes, how much? 40 ohm, 50ohm ?
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① 添付データシートのAC特性に記載されているLeakage Currentは
CY7C2663KV18-450BZI component height tolerance from PCB is required for thermal analysis. I need to know that min, typical and max height value in mm. Below drawing is given in the datasheet. Max value is given, But I could not get min and typical values from PCB to IC top by using below drawing.
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*CY7C2663KV18 - 450BZI has an internal PLL and that PLL is controlled via DOFF pin (pll turn off (active low)).
* When this part selected in the Xilinx MIG IP, it generates a qdriip_dll_off_n pin.
* In the MIG IP datasheet it is written that qdriip_dll_off_n pin turns off the internal DLL in the memory device. What is the DLL ? This DLL is PLL in the part CY7C2663KV18 - 450BZI ? This part CY7C2663KV18 - 450BZI does not contain any internal DLL, does it ? If there is no internal DLL in the part CY7C2663KV18 - 450BZI, why Xilinx MIG IP generates this qdriip_dll_off_n pin ? Or DLL and PLL is different things ? Should I connect these two pin to each - other, or not ?
Best Regards,Show Less
I could not find the VDDQ supply power consumption in datasheet. Could you provide a maximum current consumption of VDDQ of part CY7C2663KV18-450BZI ?
Also you could provide that if Vref (0.75V) draw current or not ?
I wonder that, should JTAG pins of the part CY7C2663KV18 - 450BZI be connected to the whole jtag chain of the board, in order to perform the boundary-scan test ? I mean that could I perform boundary-scan test on the this SRAM without connecting the its JTAG pins to whole JTAG chain ?
Hi to all,
We are going to use a STM32F2 with a async SRAM CY7C1041GN30-10ZSXI.
It is the first time I work with one of these and I have many many questios: trace lengths should be similar, impedance controlled .....
Do you know any document where I can get the answers for these questions and more tips to take into consideration?
Thanks in advance,