SRAM Forum Discussions
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We are using four of CY7C1069G30-10ZSXI in parallel to get a 32-bit data bus connected to a FPGA as host.
- Is it any need for length matching in the pcb layout when using these SRAM's?
- Are there any PCB design guideline documents for these types of SRAM's available?
Show LessHi,
We are using LPC4088 based custom board interfacing external nor-flash(SST39vf3201), SRAM(CY62157EV30LL) & FPGA on static memory CS3, CS1, CS0 respectively. We are using Nor-flash for code storage & execution. A custom USB bootloader is stored in internal flash & execution jumps from internal to external flash.
SRAM is used mainly for LCD buffers & LCD has dedicated DMA which reads bmps from SRAM & load into LCD display. The problem is that when I initialize SRAM according to its wait states given in the data sheet, the actual wait states I get is double of what I set. I did not understand this. Due to this it is slow and also affect the code execution.
Anyone aware of this problem. Please help.
Regards
Chaitanya.
Show LessHello,
We are using Async SRAM "CY7C1021DV33-10ZSXI" from cypress.
As per datasheet and other design guideline document from cypress, there is no length matching requirements listed.
but as it is a parallel bus, we believe there should be length matching requirements for these Address and control group and data group.
so, let us know the length matching requirements for the Async SRAMs.
Thanks and Regards
Tarang Jindal
Show LessHi,
I need to use CY7C09269V-12AXC in one of my design. Unfortunately found its obsolete now. Please help me to find a compatible alternative for that.
http://www.cypress.com/file/42961/download
Thanks,
Prem
Show LessHi all,
I want to know the differences between "CY7C1061G30-10BVJXI" and "CY7C1061G30-10BV1XI" (J or 1) ?
Are all below ordering codes drop in replacement for CY7C1061G30-10BVJXI ?
CY7C1061G30-10BV1XI
CY7C1061GE30-10BV1XI
CY7C1061GE30-10BVJXI
Thank's in advance,
Best Regards
Niklas
Show LessDear Cypress,
I am checking the CY7S1061GE30 that is entered into Custom B/D with TI hercules rm48x.
In order to use this SRAM, I need to set correct values into EMIF register.
Below captured screen is TI Halcogen HMI which generates HAL(Hardware Abstraction Layer) code.
I'm trying to find below values (ASYNC1 Timings : W_SETUP, W_STROBE, W_HOLD, R_SETUP, R_STROBE, R_HOLD).
The clock is set as 100 MHz now. so I assume that 1 cycle is 10 ns.
Even though, I've checked AC switching Characteristics of your datasheet,
I didn't catch which value is correct for below setting.
Because all values of AC switching Characteristics are less than 10 ns.
So it seems that below values are filled as 0 or 1.
For your reference, Let me attached EMIF document.
Could you kindly guide me how I calculate these?
Thank you.
TI Halcogen HMI
CY7S1061GE30 datasheet
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Please advise. Thank you.
Hi, I used CY7B138-35JC in the design, but it is obsolete now, do you have a replacement for it , which is Pin to Pin and the supply voltage is compatible ? Thank you.
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