SRAM Forum Discussions

The datasheet references ambient temperatures, both operating range and absolute maximum, but there seems to be no junction temperature information included. Specifically, is there an operating range maximum for junction temperature for the part?

I am looking for a direct drop-in replacement for CY62146VLL-70ZI. Seeing that this SRAM chip has gone obsolete, I was looking at the CY62146EV30 MoBL chip. Unfortunately, the EV30 has a different pin-out than the CY62146VLL-70ZI and am unable to go through a complete redesign of the CCA that it resides on. Any help would be very much appreciated.

We need your support to know the definition of these expressions

1- Sleep Mode option and Stop Clock option

2-Automatic power down

3-On-Die Termination (ODT)

4- Full data coherency

5- Fully asynchronous operation

6-RadStop™ Technology

We have a concern regarding “CY7C1563XV18” family which you can find on the datasheet below. Our concern is on the “Address Bus Width” feature, as we notice that this family has left and right ports with value “20” per each port. Our question is, should we take the total value of the couple of ports as “40”? or should we take it for just one port as “20” as found on “Pin Configurations” table”? Your cooperation will be greatly appreciated.

Datasheet Link: http://www.cypress.com/file/45666/download

I would like to have our schematic reviewed.  It includes CY7C1321KV18-250BZXC, interfaced with Xilinx Kintex7 FPGA.

Please let me know who I can send the schematic to.

Thanks,

Andrew

I am using CY7C1441KV33-133AXM product.

Currently, SRAM roadmap has been confirmed.

Production was confirmed by 2022.

I want to know the production schedule after 2022.

Hello,

We are using 1Mb ASYNC SRAM  CY7C1021DV33-10ZSXI in our new design.

The datasheet of this device mentioned 3 modes of write cycle on page - 9 and 10. These modes are -

1) Write Cycle No. 1 (CE Controlled)

2) Write Cycle No. 2 (BLE or BHE Controlled)

3) Write Cycle No. 3 (WE Controlled, OE LOW)

The datasheet of  2Mb part CY7C1011DV33 of this series has mentioned one extra mode i.e. - Write Cycle No. 3 (WE Controlled, OE HIGH During Write)

We want to use this "Write Cycle No. 3 (WE Controlled, OE HIGH During Write)" mode for writing the data in SRAM as there will be a continuous write in our application. so, we want to make OE# high for entire write duration.

so, please confirm that, is this  "WE Controlled, OE HIGH During Write" write cycle mode also applicable for 1Mb SRAM part - CY7C1021DV33-10ZSXI

for ref, i am attaching the WE Controlled, OE HIGH During Write" write cycle mode snapshot mentioned in 2Mb part.

Thanks and Regards

Tarang JIndal

Hello,

Customer refer to the SRAM read control by "Figure 15. Read Cycle No. 3" in the datasheet on page 12.

In this access, is it possible to read data correctly from SRAM even when "OE goes to Low before CE goes to Low"?

MCU will act the OE signal to Low about 20ns faster than CS signal to Low in worst case.

MPN : CY7C1061G/GE

http://www.cypress.com/file/46676/download

Best Regards,

Naoaki Morimoto