I am new to this IC programming but i have to use this IC for my work please give some insights about the programming of this IC....Show Less
I'm now designing the PCB with CY7C25652KV18 and XILINX FPGA. I'd like to set the trace impedance of the line between SRAM and FPGA.
According to the data sheet, the output impedance of the SRAM's output pin can be set by using RQ resistor between ZQ pin and the ground. The data sheet says that the output impedance shall be set to 0.2 x RQ. So I set the RQ to 250ohm in order to get the 50ohm trace impedance.
Then the input impedance of some SRAM's input pins are defined by On Die Termination function. In this case the input impedance shall be set to RQ/3.33 or RQ/1.66 according to data sheet. For both case, the input impedance cannot be set to 50ohm if RQ = 250ohm. In other words, it is impossible to have same impedance value for the input and output impedance of the SRAM pins. I found the similar discussion in this forum. That is On-Die Termination ZQ value?
On the other hand, there is the description "Cypress Packages are routed to obtain all traces to 50 ohm ± 10%. All traces must be routed to have 50-Ω impedance and should have no impedance discontinuities." in "AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide" It says that the input and output impedance of the SRAM is the same 50ohm.
Therefore I'm now much confused. Which is correct, AN4065 or the content of the discussion? Or do I misunderstand anything?Show Less
We would like to confirm the standby condition of MoBL SRAM.
What voltage is indicated by "Vin" on page 6 in the data sheet of CY62167EV30?
Can we understand that "Vin" means input voltage of A[0:10] and I/O[0:15]?Show Less
AN6081 recommends using older SRAM devices for interfacing to legacy 5V processors which require CMOS level Vih min (e.g. use CY7C1021BN instead of CY7C1021D).
However the CY7C1021BN data sheet only specifies Voh min as 2.4V min @ Ioh= 4mA.
Can such part actually be used with a legacy 5V processor?Show Less
AN54908 calculation shows 65nm having a lower LSBU factor. In past experience smaller die have greater error. Are there improvements that accounts for the lower LSBU in the 65nm versus 90nm?Show Less
36MbのQDRⅡを2 Word Bust Modeで使用しています。
QDRⅡ+への置き換えを検討していますが、2 Word Bust Modeがありません。
72MbのQDRⅡ+には、2 Word Bust Modeがありますが、