SRAM Forum Discussions
Dear Sir or Madam,
I plan to use the CY62167ELL in a 8/16 bits application.
For example I will need to :
1/write a 16 bit word using IO15:0
2/read both bytes of this same word using IO7:0
The BYTE# signal seems the feature I need, however it is poorly documented in the datasheet (just a footnote!).
Because of that I have some questions :
-Is it OK to dynamically change the BYTE# signal to access the stored data in both 8 and 16 bits modes ?
-When I look at other devices with a similar feature, IO15 is labelled as "A-1" and clearly stated as the LSB address input : thanks to that, it is clear that this pin controls which byte of the word is served on IO7:0, and that all the other address signals just need to be the same as 16 bit access.
The CY62167ELL datasheet uses "I/O15/A20", so I understand that it is actually the MSB address input : the signal controlling which byte of the word is served would be A0 (the LSB). If it is true, then my application would have to shift all the addresses signals between each word and byte accesses, which is a no-go for me.
Could it be an error in the datasheet ? (I hope so...)
-I would like to know which byte of the 16 bit word is served during 8 bit access ? For example : Lower byte when A-1 is low, and higher byte when A-1 is high.
All of this would be a great addition to the datasheets.
Show LessDear engineers of cypress,
I have met some issues when using the CY7C1470V33.I have past the verilog model test ,but no data could be written in the sram on the board.During the period of testing ,I have set the output of fpga to the pin "zz" is 0 ,1 and non-connnected,the phenomenon is still no changed and no data were written in the sram.I found the test on the datasheet the voltage of pin "zz" is less than 0.2 v.
So what is the low voltage standard value of the pin "zz"?would you please give me some advices about the question?
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HI,
I am using CY7C1041G30-10ZSXI SRAM which is interfaced with microsemi samrt fusion 2 FPGA. In interfacing the part to FPGA, I am not sure any kind of termination (like series resistor, as of now no terminations are considered as it cmos output and inputs) is required here to reduce the reflection between the device other than length matching (+/-10mils in FR4 board) and impedance (50+/-10%) control in PCB. Maximum operating frequency considered as 100MHz
Kindly recommend any terminations are to be considered for this particular interface and let me know if any other considerations to be taken for reducing the reflection.
Show LessHi, I cannot seem to find the Junction to Board Thermal resistance for this SRAM (CY62167GE30-45ZXIE 65 nm ). In the temperature specification pdf the Theta jb parameter is listed as provided upon request.
Has this question already been asked?
Thank you in advance,
Léo Coïc
Hi all, I need a VHDL model for SRAM CY7C1381KVE33. On Cypress site I have found only the Verilog one. Anyone knows if I may download (or request) an equivalent VHDL model? thanks a lot
Show Lesspart number CY7C4285V-15ASI, the pin 55 for this part is GND part, but it is open, it is not connect with the wafer. would this be an problem to use the part ? will this cause the reliability problem?
Show LessHi. Cypress
In the web, I can't find out this PN CY7C1460KV33-200AXC Product Qualification Report in website of Device Qualification Reports?would you help to provide it, but others PN can find like cy7c1009d-10vxit https://www.cypress.com/part/cy7c1009d-10vxit
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