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SRAM

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mark63122
SRAM
Hello, We are re-spinning a design that uses a CY62147EV30LL-45BVXI SRAM - Asynchronous Memory IC 4Mb (256K x 16) Parallel 45 ns 48-VFBGA (6x8). Wonde... Show More
Harpreetsingh
SRAM
I am using CY62167EV30LL, I want to share this memory between 2 microcontrollers.  Query 1: can we share it? If yes, please suggest the solution. I ha... Show More
ErezN
SRAM
Hi, CY7C1168KV18 contain bidirectional data bus DQ. The DQ port has build in serial termination but lack of active pull-up termination (for receiving ... Show More
ErezN
SRAM
Hi, I can't find in the data-sheet CY7C1168KV18 Vref current consumption. In the application not it is recommended to add to Vref decoupling capacitor... Show More
Sne
SRAM
Hello, in this post "https://community.infineon.com/t5/SRAM/QDR-IV-memory-controller-for-Zynq-Ultrascale/m-p/266947" infineon says that there is a int... Show More
MAO
SRAM
I think there are synchronous and asynchronous SRAM of Cypress, but I would like to know the main lineup of synchronous SRAM such as serial and parall... Show More
paulj
SRAM
Hello Infineon, I'm conducting academic research in methods of reliability analysis with help of the 1021 SRAM series from Cypress, and I have a few q... Show More
htajalli
SRAM
This SRAM :CY62167EV30LL-45BVI is used in our product and no longer available. I appreciate your help to find a replacement for it.  Ideally a drop-in... Show More
MAO
SRAM
Assert CS(chip enable) and OE (output enable) pinsIs it possible to continuously read the data signal by switching the address signal? (Page Lead) Show More
Saidev
SRAM
Hi, I'm currently working on CY7C1471BV33-133BZI SRAM. Interfaced with MPC5777C power architecture via EBI. I'm using Chip select 0 for communication,... Show More
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SRAM

Discussion forum for SRAM related topics.