SRAM Forum Discussions

Hello,

I have two thermal questions regarding CY7C2665KV18 (144-Mbit QDR II+)

1. Is the provided thermal resistance JC of 2.1 °C/W junction-to-case-TOP, or junction-to-case-BOTTOM? If it is the top, do you have the junction-to-case-BOTTOM value?

2. According to the "Test Conditions", it states the device was socketed onto a PCB. Does the provided JB (junction-to-board) value of 9.34 °C/W include the additional socket resistance? (i.e. we are not using a socket in our application. We are soldering the device directly to a PCB. Does this mean we cannot use the data sheet provided JB value?)

Thank you

I use CY7C1470BV 33.
There is a time when it doesn't work, so I want to stop the clock input to reduce the power consumption. Is there any problem?
The MODE pin is fixed "L" and cannot be set to SLEEP MODE.

Hello!

We have been using the CP62167EV30LL-45BVXI memory on our modules since 2014.

We were affected by the AN66311 in 2014
"TIMING RECOMMENDATIONS FOR BYTE ENABLES AND CHIP ENABLES IN MOBL (R) SRAMS - AN66311"

After this bug was fixed by Cypress and we received new CP62167EV30 components, the error on our modules disappeared.

Until now in 2021.

Memory errors are now increasingly occurring on our assemblies during the final inspection, failure rate approx. 50%. After asking us, we were able to determine that Cypress has changed this SRAM from 90nm technology to 65nm technology.

Hello!

I looked at the data sheet and compared it with the old one and couldn't see any significant changes. An analysis of the memory accesses, timing, etc. on the defective assemblies has not been successful either.

If defective modules from production are equipped with the previous 90nm CP62167EV30LL-45BVXI, then they will function properly again.

Could it be that by changing the technology from 90nm to 65nm, the old bug from AN66311 was redesigned.

I am grateful for a quick answer.

greeting
Max power

Please let us know process rule (nm) of below 2 parts;

QDR4：CY7C4142KV13-933FCXI
QDR2：CY7C2265KV18-550BZXI

Hello,

I came across this Knowledge base article in Cypress website and thought it will be very useful.   

It talks about the Address pin numbering in QDR II SRAMs. Do have a look at it.   

thanks

jackyjoy

Hello,

The QDR datasheet recommends that during power up sequence to apply Vdd before Vddq. Is it mandatory during the power up sequence to apply Vdd before Vddq?

thanks

alexsunny

I want to use QDRIV: CY7C4142KC13 as a memory for my Xilinx versal AI device.

The FAE of Xilinx said their hardware IP doesn't support QVLDA0,1&QVLDB0,1.

So could you tell me how should I connect QVLDA0,1&QVLDB0,1 rightly when these pins are not used?
Thanks very much.

Could you please provide the requested information for below parts?

When is Production start year?

Is this part is in production now?

Is this part is EOL ? please provide the LTB and LTS date.

Is this part supported min 7 years from now? if not please mention the No. of the years supported?

Is the current technology used in the part supported for NPI projects?