I believe there are errors in the datasheet for P/N CY7C1380D. Please check
the following issues:
1. The timing diagrams on pages 24 and on are visually corrupted. The hatching used
to indicated don't care is only partially visible which makes the diagram confusing.
2. The "Functional overview" section describes the various access patterns for using the device.
However, the descriptions don't match up with the waveforms (even disregarding the visual issues).
For example, the description of "Single Read Accesses" asserts that during the first cycle of an ADSP_N read, the write signals GW_n/BWE_n must be deasserted. But the diagram marks them as Don't Care.
I compared both the diagram and the description to a newer datasheet for P/N CY7C1381KV33
and neither problem appears there. I believe that in (2) above the datasheet verbal description is wrong (indeed, it does not match the one in CY7C1381KV33). And the corrupted diagram seems
to be identical to the one in the newer datasheet, except for the missing hatched lines.
I've been unable to contact support so I'm hoping they keep an eye on reports via this channel.
In the CY7C1380KV33 data sheet which Electrical and Switching parameters are tested at temperature and which are only tested at lab ambient? Are all components subjected to temperature testing or are only a sample per lot, date code... tested at temperature?Show Less
Assert CS (chip enable), and OE (output enable) pins Is it possible to continuously read the data signal by switching the address signal while keeping it? (Page lead)Show Less
Good morning, I am currently working on the development of a product which includes CY62157EV30LL-45ZXA SRAM.
We are using the device in 8-bit data mode, using address pins A0-A19, with BHE and BLE tied high, and BYTE tied low.
In many areas of the datasheet, it is specified that '29. During this period, the I/Os are in output state. Do not apply input signals.'
We understand this that if the I/Os are in an output state, and we drive a voltage into these pins at this time - it is possible that we may physically damage the memory. We are not comfortable shipping a product that could be damaged by firmware - validated firmware or not.
Are we understanding this correctly? And in such a case, would Infineon recommend the use of series resistors on the data lines to stay within the 20mA 'output current into outputs (LOW)' specification, within the maximum ratings section of the datasheet?
Many thanks in advance
I checked the data sheet, but it was not disclosed, so please let me check.
Are internal pull-up resistors installed on each of the control(CE1/OE/WE/BLE/BHE), address, and data pins?
Using the memory CY7C1380D-167AXI, I'm looking for some information about the SEU and MBU rates of the memory.
Newer parts datasheets have a “Neutron Soft Error Immunity” table included but this older part does not have that information included.
Hi ,in my board, i use Xilinx IP to Access CY7C2665KV18.
when in write process, BWS signal looks strange, maybe with ODT Problem.
The yellow signal is WPS signal
The green signal is BWS signal
When WPS is high, BWS signal can toggle around 750mV
But when WPS is Low, in write process, BWS signal can't higher than 750mV
We've been using 62147 for years with no problems. Coupled with STM32F207IGH6. Our design allows for 62157 to be placed instead so we have A18 available and tie CE2 high. There is no other memory on the bus. With 62157 our memory test reports all kinds of different failures. In summary the kinds of effects are:
- adjacent words mostly get repeated when being read consecutively. Possible cross-talk between A0 and A1 but its not consistent as sometimes both words do get read correctly
- writes sometimes seem to fail. For instance if we pattern fill the memory and then zero fill, sometimes some of the locations retain their previously written values
- over time a zero filled memory space will gradually get corrupted with what seem like random values
I suspect that this is all due to some basic hardware issue or FSMC configuration that doesn't show with 62147 but the datasheets seem identical in all respects.
We are re-spinning a design that uses a CY62147EV30LL-45BVXI SRAM - Asynchronous Memory IC 4Mb (256K x 16) Parallel 45 ns 48-VFBGA (6x8). Wondering if there is a newer part to use? Looks like the CY62147G30-45BVXI is a drop-in. Also looks like the ERR pin version, CY62147GE30-45BVXI would also work.
What would you recommend to put as the primary part on the parts list. And what other parts can we list as drop-in substitutes.