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SRAM

yaya_4678691
New Contributor

Dear engineers of cypress,

        I have met some issues when using the  CY7C1470V33.I have past the verilog model test  ,but no data could be  written in  the sram on the board.During the period of testing ,I have set the output  of fpga to the pin "zz" is 0 ,1 and non-connnected,the phenomenon is still no changed and no data were written in the sram.I found the test on the datasheet  the voltage of pin "zz"  is  less  than 0.2 v.

       So what is  the low voltage standard  value of  the pin "zz"?would you  please give me  some advices about the question?

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi,

As the datasheet states the VIL value ( Input Low Voltage) value for zz pin or any pin for the device is 0.8V for a 3.3V device. Since the MPN you are mentioning also has a errata associated with it i request you to go through it once in the datasheet. The pin needs to be at Low or High voltage as per the requirement but do not leave the pin as unconnected/ floating as it can lead to errors. Can you once tie the ZZ pin externally to GND and check

To debug your issue can you kindly check and provide us

1) The power up and power down waveform for the device.

2) The wave form for the ZZ pin along with other control signals like WE, CE, OE etc for a read/write operation on the device.

Thanks,

Pradipta.

View solution in original post

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3 Replies
PradiptaB_11
Moderator
Moderator

Hi,

As the datasheet states the VIL value ( Input Low Voltage) value for zz pin or any pin for the device is 0.8V for a 3.3V device. Since the MPN you are mentioning also has a errata associated with it i request you to go through it once in the datasheet. The pin needs to be at Low or High voltage as per the requirement but do not leave the pin as unconnected/ floating as it can lead to errors. Can you once tie the ZZ pin externally to GND and check

To debug your issue can you kindly check and provide us

1) The power up and power down waveform for the device.

2) The wave form for the ZZ pin along with other control signals like WE, CE, OE etc for a read/write operation on the device.

Thanks,

Pradipta.

View solution in original post

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yaya_4678691
New Contributor

Thank you for your attention.I tried to put the pin zz  connect to the ground on the board,the phenomenon is no changed.

The hardware situation determined that the record for power up and power off of the device cannot be got.The ila waveform of the chipscope and the hardware design  is followed as below.

30488b15b10048326974756646a91eb.jpg

QQ图片20200409000446.png

When writting data on the device,the right data could be found on dq bus.However the data was still the last writting data on the  dq  bus when reading.I would feel grateful if you could provide some advices for me.

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yaya_4678691
New Contributor

Thank you very much. The probelem has been solved.The reason for this  question  is that the version of schematic design is not updated as soon as possible.The product of  CYPRESS is good.

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