SRAM and legacy 5V processors

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Anonymous
Not applicable

AN6081 recommends using older SRAM devices for interfacing to legacy 5V processors which require CMOS level Vih min (e.g. use CY7C1021BN instead of CY7C1021D).

However the CY7C1021BN data sheet only specifies Voh min as 2.4V min @ Ioh= 4mA.

Can such part actually be used with a legacy 5V processor?

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1 Solution

Hi Antonio,

You are correct. While we measure VOH at a specific IOH, the CY7C1021BN device is based on a very old technology and has very strong buffers for IO. So these parts should not suffer significant speed penalty.

Perhaps IBIS simulation will be the best method to verify this (link here)

I am not sure what package you are looking for, but if your design allows for, will you be willing to migrate to a higher density latest generation SRAM?

This device is truly designed for VOH of 5V

http://www.cypress.com/part/cy7c1041g-10zsxi

Regards,

Nilesh

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4 Replies
PradiptaB_11
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500 replies posted 250 solutions authored 250 replies posted

Hi Antonio,

The older generation parts are compatible with both TTL I/O standards and CMOS I/O standards. It is also explained in the Application Note as well to which we are referring.

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Thanks,

Pradipta.

Anonymous
Not applicable

Hello Pradipta,

thank you for your reply.

So, as I understand, although the CY7C1021BN data sheet does not specify VOH (min) = 4 V I should trust AN6081.

I still see a gray area, since:

1) the VOH (min) = 4V figure in AN6081 makes no reference to an IOH value

2) I assume all timing specification in the CY7C1021BN data sheet refers to VOH (min) = 2.4V since this is the only VOH (min) value mentioned in such document.

Although a CMOS input load is basically a capacitance, so we can expect to reach VOH (min) = 4 V "at some time" even if such value is only guaranteed at a very low IOH current, I expect timing to be somewhat impacted.

Can you elaborate a bit on this point?

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Hi Antonio,

You are correct. While we measure VOH at a specific IOH, the CY7C1021BN device is based on a very old technology and has very strong buffers for IO. So these parts should not suffer significant speed penalty.

Perhaps IBIS simulation will be the best method to verify this (link here)

I am not sure what package you are looking for, but if your design allows for, will you be willing to migrate to a higher density latest generation SRAM?

This device is truly designed for VOH of 5V

http://www.cypress.com/part/cy7c1041g-10zsxi

Regards,

Nilesh

Anonymous
Not applicable

Hi Nilesh,

thank you.

I believe everything is clear now.

Concerning the alternative part you suggest, we will definetely take a look.

best Regards

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