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Saidev
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Hi,

I'm currently working on CY7C1471BV33-133BZI SRAM. Interfaced with MPC5777C power architecture via EBI.

I'm using Chip select 0 for communication, I also attached the schematic for reference.

Here my problem I'm able write data in SRAM but not in a particular address , When I try to write in one address data being written in all address. Is there any configuration I need to do?

kindly please respond and help me out with this. 

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ritwicksharma
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Moderator 100 replies posted 50 solutions authored First question asked
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Hi @Saidev,

 

> May I know what is JP14 in your schematic. I believe it is a switch connecting CE3# to GND, right?


> For single write, please make sure the control signals are the same as mentioned in the Truth Table (highlighted in yellow). Kindly refer to the datasheet (single write access section) for more details.

ritwicksharma_0-1645008852195.png

I suspect that you are making ADV/LD# line high after a single write operation, which on subsequent clock rise, increments the burst counter, and hence burst write is happening.



Thanks,
Ritwick

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Saidev
Level 1
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yes, JP14 is for CE3 to Gnd.

I'm not making control pins high or low I just configured the EBI and it will do the rest of the operation as per the configuration. I also monitored the required pins it is working fine. Do I need to control A0 & A1 pins using controller GPIO. As per schematic I connected Address pins, Is that fine. 

 Do you have any reference schematic for this particular SRAM it will be helpful to proceed further.

Thanks in advance

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ritwicksharma
Moderator
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Hi @Saidev,

 

For reference schematic design for NoBL SRAMs, please click here.

 

Thanks,

Ritwick

 

Thanks,

Ritwick

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Saidev
Level 1
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Thank you @ritwicksharma 

reference schematic is very useful. however I want to know what connections to be given to  pins A0 & A1. From microcontroller either address pins or GPIO pin which one ? 

Thanks 

sai

 

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
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Hi @Saidev,

 

I am not sure what you exactly meant by address pins. Are these the dedicated pins for controlling address pins? If yes, then you can use it as it will be the output lines for the MCU and input for FRAM. A0 and A1 will be connected in a similar manner as the rest of the address pins. Internally, the difference is just that A0 and A1 lines go into a burst counter. So if the ADV/LD# is made high after a single write operation, then the subsequent clock rise increments the burst counter, and hence burst write happens.


> Also, in the schematic, I see only A0, A1, A_0, A_7, A_8, A_13, and A_14 are connected. What about the rest? Are they left unconnected? And what do the below arrows indicate? Are they indicating input/output directions?

ritwicksharma_2-1645528945761.png

ritwicksharma_3-1645528945565.png

 

Thanks,

Ritwick

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Saidev
Level 1
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For other address pins Output from latch pins are connected C0, C1.., D1, D2... etc.

Used to write data in muxed configuration.

Following schematic is the reference we used.

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
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Hi @Saidev,

 

You missed answering the below questions. Please answer them.
What do the below arrows indicate? Are they indicating input/output directions?

ritwicksharma_0-1646044957997.png

 

ritwicksharma_1-1646044958089.png

 

Thanks,

Ritwick

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