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SRAM Forum Discussions

Qu19_4750531
Level 2
Level 2

Hello,

I am trying to interface CY7C1061G30 SRAM with Infineon controller. 

I was wondering Is there a device ID or any other ID which i can read to confirm communication with SRAM ?

Also Is there a user manual available for this part ?

Any feedback is appreciated.

Thanks

Best Regards

Query1920

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1 Solution
PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi,

There is no device ID associated with SRAM. For testing the SRAM communication you may read and write a known test pattern.

There is no specific user manual for SRAM, we have all the required information in the datasheet which provides detailed information on all the SRAM operations and how to operate the SRAM.

Let us know if you are facing any issues or have any concerns and we will sort it out.

Thanks,

Pradipta.

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3 Replies
PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi,

There is no device ID associated with SRAM. For testing the SRAM communication you may read and write a known test pattern.

There is no specific user manual for SRAM, we have all the required information in the datasheet which provides detailed information on all the SRAM operations and how to operate the SRAM.

Let us know if you are facing any issues or have any concerns and we will sort it out.

Thanks,

Pradipta.

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Qu19_4750531
Level 2
Level 2

Hi Pradipta,

If i perform read operation prior writing any known pattern into SRAM then what should i expect 0x00's or 0xFF's ?

Thanks.

Best Regards,

Query1920

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PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi,

The SRAM is volatile memory and will lose all data during a power cycle or power down condition. During a power up how the SRAM cell will behave is difficult to predict. Some memory locations may power up with zero and some with one. It is random process and cannot be predicted. So you can consider the SRAM to contain garbage value after a power up.

Thanks,

Pradipta.

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