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Does cypress have a memory controller IP for Xilinx's Zynq Ultrascale+ devices?
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Memory SRAM
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Hi,
You can refer to the Xilinx documentation for your requirement.
Thanks,
Pradipta.
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Hi,
You can refer to the Xilinx documentation for your requirement.
Thanks,
Pradipta.
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Hello Pradipta,
I'm spoke with Xilinx about their QDR-IV memory controller for their Zynq Ultrascale devices but they could not confirm support for the depth expansion per section 9 of Cypress's QDR-IV Design Guide AN84060. They referred me to Cypress to see if your team has provided an QDR-IV controller that supports depth expansion. Can I infer from your response that Cypress does not have a QDR-IV memory controller for Zynq Ultrascale+ devices? Do you know if Xilinx's memory controller will support depth expansion?
Thanks for your help,
Steve
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Hi Steve,
We have one controller for internal use but it was developed to use one memory at a time. For depth expansion you will require multiple lbk signals. I could not find this in the Xilinx IP or in the document. You may have to create/write some soft IP to do this.
Thanks,
Pradipta.