SRAM

[calliope]

We are using a CY7C1645KV18-400BZXI QDR-II+ for one of our designs with an 1.8V I/O supply, which is supported as clearly stated in the Datasheet.

We discovered that the Xilinx IP for the QDRII doesn’t support 1.8V. We asked for a solution and Xilinx proposed a workaround that would permit us to generate a bitstream with 1.8V I/O and it still didn’t work.

Is there another Soft IP by Infineon that we could use to drive our QDRII+? Or another way to generate a bitstream for 1.8V I/O?

[PradiptaB_11 · Accepted solution]

Hi @calliope ,

Currently we do not have a IP for this. I will check within the team again for any solutions for this issue and update the same if there is one from our side.

Thanks,

Pradipta.

[calliope]

Hi @PradiptaB_11 ,

Thank you for your prompt reply. We read that you could provide a Synchronous SRAM memory controller that can be integrated as soft IP in Xilinx FPGAs. There is nothing compatible with our problem?

Best,

Calliope