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tonytelemisis
Level 1
5 replies posted First reply posted First question asked
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We've been using 62147 for years with no problems. Coupled with STM32F207IGH6. Our design allows for 62157 to be placed instead so we have A18 available and tie CE2 high. There is no other memory on the bus. With 62157 our memory test reports all kinds of different failures. In summary the kinds of effects are:

- adjacent words mostly get repeated when being read consecutively. Possible cross-talk between A0 and A1 but its not consistent as sometimes both words do get read correctly

- writes sometimes seem to fail. For instance if we pattern fill the memory and then zero fill, sometimes some of the locations retain their previously written values 

- over time a zero filled memory space will gradually get corrupted with what seem like random values

I suspect that this is all due to some basic hardware issue or FSMC configuration that doesn't show with 62147 but the datasheets seem identical in all respects.

CY62157EV30LL-45BVXI

CY62147EV30LL-45BVXAT

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1 Solution
ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
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Hi @tonytelemisis,

 

I see you are always switching PD, PE, PF, and PG GPIOS at 100 MHz which is wrong. You must comply with the datasheet specs for the desired result.

ritwicksharma_0-1654684910381.png

E.g., you are performing a read operation (OE# controlled). tACE is 45 ns (min), so you are not supposed to switch any address pins before 45 ns, and also, you are supposed to read the result after 45 ns for the valid data, and you are switching pins @ 100 MHz, i.e., 10 ns. So, please meet every timing spec mentioned in the datasheet (pg#7).

 

Thanks,

Ritwick

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ritwicksharma
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Moderator 100 replies posted 50 solutions authored First question asked
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Hi @tonytelemisis,

 

> Is your application automotive?

 

> On how many devices did you observe this kind of behavior?

 

> Could you please share the schematic of the memory portion? Our design guidelines for battery-backed asynchronous SRAMs are explained in AN44517.

 

Thanks,

Ritwick

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tonytelemisis
Level 1
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Hi Ritwick,

Application is IIoT, not automotive. The memory is permanently powered during all the tests I mentioned. I observe this behaviour on all our devices using the 62157 but not with the 62147.

tonytelemisis_0-1653908046982.png

A19,A20 not used and are for future use with bigger memory.

Is the lack of a weak pullup to 3v3 on CE2 a potential design issue?

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ritwicksharma
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Moderator 100 replies posted 50 solutions authored First question asked
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Hi @tonytelemisis,

 

Is the lack of a weak pullup to 3v3 on CE2 a potential design issue?

> Could you please test it by connecting a pull-up resistor to CE2 and let us know the result?

 

Thanks,

Ritwick

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tonytelemisis
Level 1
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Hi, that's unfortunately not possible without spinning a new board.

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
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Hi @tonytelemisis,

 

Could you please share the read and write scope shots for a failing device (CY62157EV30LL-45BVXI) and an old passing device (CY62147EV30LL-45BVXAT)?

 

Thanks,

Ritwick

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tonytelemisis
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Unfortunately impossible as the tracks are not accessible

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
Moderator

Hi @tonytelemisis,

 

Could you please let us know at what speed you are performing read/write operations?

 

Thanks,

Ritwick

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tonytelemisis
Level 1
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Level 1

Hi Ritwick,

Are these definitions from our project what you need?

 

/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 |
| PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 |
| PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+
| PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 |
+-------------------| PE12 <-> FSMC_D9 |
| PE13 <-> FSMC_D10 |
| PE14 <-> FSMC_D11 |
| PE15 <-> FSMC_D12 |
+--------------------+
*/

/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR |= 0x00000078;

/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcccccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xaaaa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xffff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;

/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xcccccccc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaaaaaa;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffffff;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;

/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;

/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;

/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;

/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;

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ritwicksharma
Moderator
Moderator 100 replies posted 50 solutions authored First question asked
Moderator

Hi @tonytelemisis,

 

I see you are always switching PD, PE, PF, and PG GPIOS at 100 MHz which is wrong. You must comply with the datasheet specs for the desired result.

ritwicksharma_0-1654684910381.png

E.g., you are performing a read operation (OE# controlled). tACE is 45 ns (min), so you are not supposed to switch any address pins before 45 ns, and also, you are supposed to read the result after 45 ns for the valid data, and you are switching pins @ 100 MHz, i.e., 10 ns. So, please meet every timing spec mentioned in the datasheet (pg#7).

 

Thanks,

Ritwick

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tonytelemisis
Level 1
5 replies posted First reply posted First question asked
Level 1

Thanks Ritwick, that makes perfect sense! We will try it. Odd though that we never had any problems with CY62147 using the same parameters

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