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SRAM Forum Discussions

Anonymous
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Anonymous
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Hi,

   

 

   

I have attached a document which explains how read and write operation will take place when ADSP#, ADSC# and ADV# are permanently connected to certain logic levels.

   

I hope this would be useful to you.

   

Regards,

   

Asha

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Anonymous
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I'm also interested in knowing how the SRAM behaves with the ADSP and ADSC pins tied low.  But, I can't not see any attachment in the previous post.  Can someone please repeat the answer.

   

Thanks,

   

Steve

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Anonymous
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Hi,

   

When /ADSP and /ADSC are both asserted, only /ADSP is recognised. Therefore if both pins are tied low, then only ADSP is recognised.

   

Regards,

   

Dev

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Anonymous
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Hi,

   

I stumbled across this post because I was researching how /ADSP and /ADSC work. I need to replace asynchronous sram with synchronous in an existing design and I do not have enough spare pins to feed these pins. I also do not need the burst feature.

   

Is my understanding correct that when /ADSP is tied low I can just apply addresses to the address bus and read/write data with the usual control pins I got from my asynchronous SRAM?

   

@asha I can't see any attached document..

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