PCB design considerations for CY7C1069G30-10ZSXI

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Anonymous
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We are using four of CY7C1069G30-10ZSXI in parallel to get a 32-bit data bus connected to a FPGA as host.

- Is it any need for length matching in the pcb layout when using these SRAM's?

- Are there any PCB design guideline documents for these types of SRAM's available?

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Hi Lars,

You should follow length matching for the signals (Address, data and control)

The reason being, these devices might operate at 75 or 100MHz (max) and depending on the controller setup times, there might be scenarios where the delay in longest line might case incorrect data sampling during read or incorrect writes.

Even in our internal system designs, we prefer to have length matched tracks.

The Speeds are slow, but its the edges of control and data lines that might result in failures if falsely classified as logic 0 or 1.

Hope this answers your query.

Regards,

Nilesh

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