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SRAM

Anonymous
Not applicable

We are using four of CY7C1069G30-10ZSXI in parallel to get a 32-bit data bus connected to a FPGA as host.

- Is it any need for length matching in the pcb layout when using these SRAM's?

- Are there any PCB design guideline documents for these types of SRAM's available?

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1 Solution
NileshB_06
Employee

Hi Lars,

You should follow length matching for the signals (Address, data and control)

The reason being, these devices might operate at 75 or 100MHz (max) and depending on the controller setup times, there might be scenarios where the delay in longest line might case incorrect data sampling during read or incorrect writes.

Even in our internal system designs, we prefer to have length matched tracks.

The Speeds are slow, but its the edges of control and data lines that might result in failures if falsely classified as logic 0 or 1.

Hope this answers your query.

Regards,

Nilesh

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5 Replies
PradiptaB_11
Moderator
Moderator

Hi,

We have a general document regarding this. I am providing it below.

http://www.cypress.com/file/38651/download

Thanks and Regards,

Pradipta.

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Anonymous
Not applicable

Hi!

Thanks for your response!

I have already seen this document and it does not provide any information about length matching.

Should I interpret this that length matching is unnecessary at these speeds?

The individual trace lengths of all data bus, address bus and ctrl signals are now without any matching, in the range of approximately 30-130mm.

Do you think that is ok?

Thanks and Regards,

Lars-Olof Sjoberg

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NileshB_06
Employee

Hi Lars,

You should follow length matching for the signals (Address, data and control)

The reason being, these devices might operate at 75 or 100MHz (max) and depending on the controller setup times, there might be scenarios where the delay in longest line might case incorrect data sampling during read or incorrect writes.

Even in our internal system designs, we prefer to have length matched tracks.

The Speeds are slow, but its the edges of control and data lines that might result in failures if falsely classified as logic 0 or 1.

Hope this answers your query.

Regards,

Nilesh

View solution in original post

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Anonymous
Not applicable

Hello,

I have a similar issue with my design incorporating two or four CY7C10612G30-10ZSXI SRAMs. I want to use a single address bus, but combine multiple data busses to create a 32 or 64-bit interface. I have read the SRAM board design guidelines, but as the original poster has pointed out, they don’t cover using multiple SRAMs in one design.

Are there any other relevant documents or sample designs that would help?

Thanks in advance,

Will

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NileshB_06
Employee

Hi Will,

We dont a ready reference but perhaps you have look at figure 7 of this application note: http://www.cypress.com/file/141291/download

It is called width expansion of memory.

Regards,

Nilesh

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