Hi
I'm working on interfacing cy7c1370d with spartan 6 fpga. In the data sheet its specified that the output buffers are tristated automaticaly during the 2nd cycle of the write operation where the data is presented on the DQ lines . but in the switching waveform of the datasheet at one clock transition the OE_n is high for half of the clock duration . Do i need to do the same while writing into the device ? please help...
Solved! Go to Solution.
Hi Chaitu,
DQs/DQPs are tristated when --> (WE# enabled) OR (Chip is disabled) OR (OE# is disable)
So, DQs/DQPs are automatically tristated during the data portion of a write cycle regardless of the state of OE#
OR
you can have proper OE# level during the status change, like when status changes from read to write then OE# should be disable and from write to read OE# should be enable.
You can use both option according to your convenience.
I hope this clarifies your concern.
Thanks,
Prit