The most popular/effective termination scheme for QDRII/II+ SRAMs is a pull up resistor (50ohms) to Vtt (Vddq/2).
What if the termination scheme is not implemented ? say in case of interfacing cy7c1350d which is available in 3 speed grades of 165,200,225 Mhz
and the traces are at max 1 inch in length .. so do i need to operate it at much slow speeds ?
and can i go with speeds other than the available grades by changing the input clock ??
What if the termination scheme is not implemented? Say in case of interfacing cy7c1350d which is available in 3 speed grades of 165,200,225 MHz
The termination scheme used to overcome impedance mismatch depends on the application. If the termination scheme is not there then your signal will take some time to stable and this can cause signal overshoot, undershoot, and ringing.
And the traces are at max 1 inch in length... So do I need to operate it at much slow speeds?
No, you don’t need to operate it at slow speed.
And can I go with speeds other than the available grades by changing the input clock??
Yes, you can operate our Sync SRAMs using other frequency, which should be less than the maximum frequency described in the datasheet of the respective product.
Is there any situation that we can eliminate termination resistors, considering operating frequency, maximum trace length and other characteristics of the PCB?
For instance, lets assume that:
Maximum operating frequency = 250MHz (DDR)
Maximum trace length between SRAM and FPGA = 4 cm
PCB material: FR-4 (Dielectric constant = 4.35 @ 500 MHz)
In this case signal wavelength:
lambda = c / [ sqrt(dielectric_constant) * max_operating_frequency ]
= 3e8 / (sqrt(4.35) * 500e6) = 0.29 m = 29 cm
If there is no termination, data signals coming from FPGA will reflect from the inputs of SRAM; however maximum trace length (4 cm) is significantly smaller than wavelength (29 cm) of the data signal. Do we still have to consider transmission line effects?
On the other hand, we may have to take into account data set-up and hold times of SRAM or rising - falling time of FPGA.
Can you explain how to calculate if there is a case that termination resistors can be removed?
The best way to eliminate termination resistor is to perform signal integrity simulation. We provide IBIS models for all our Sync SRAM part. By inserting your board specifications (trace length, vias etc.) and the respective IBIS model, you can perform the signal integrity simulation. If the signal strength looks good without any termination resistor then you can eliminate them otherwise please simulate it with termination resistor to get good signal quality.