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I am using CY62167EV30LL, I want to share this memory between 2 microcontrollers.
Query 1: can we share it? If yes, please suggest the solution.
I have thought to share half address line between the two microcontroller.
Other way around to mux the address line between the two controller and separate data lines for each controller.
Please suggest the solution.
Solved! Go to Solution.
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Hi @Harpreetsingh ,
1) If you want to share the memory between two processors one way is to give access to both the processors separately. Now if the data is also shared meaning say processor A writes some data in the memory and processor B wants to read this data then you will also need to take care of the cache coherency issue. This is done to ensure that processor B has access to latest written data in the memory. If both the processor work independently of one another then you can ignore the cache coherency algorithm implementation.
2) If you want to provide a dedicated section of the memory to both the processors say top half to processor A and lower half to processor B then you can fix the logic level for the most significant address bit. You can fix the logic level to 1 for processor A and 0 for processor B.
Thanks,
Pradipta.
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Hi @Harpreetsingh ,
I have one question, are you looking to provide separate memory locations to the two microcontrollers (form the memory) or is it okay if the two microcontroller share the entire memory and is able to read and write to any locations.
Thanks,
Pradipta.
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Hi @PradiptaB_11,
Both will work. Would prefer to have cost effective solution. Please suggest both options.
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Hi @Harpreetsingh ,
1) If you want to share the memory between two processors one way is to give access to both the processors separately. Now if the data is also shared meaning say processor A writes some data in the memory and processor B wants to read this data then you will also need to take care of the cache coherency issue. This is done to ensure that processor B has access to latest written data in the memory. If both the processor work independently of one another then you can ignore the cache coherency algorithm implementation.
2) If you want to provide a dedicated section of the memory to both the processors say top half to processor A and lower half to processor B then you can fix the logic level for the most significant address bit. You can fix the logic level to 1 for processor A and 0 for processor B.
Thanks,
Pradipta.
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Regards,
Harpreet Singh