SRAM

[Anonymous]

        Hi The IOstandards of the memory of the qdrll+.   

[PriteshM_61]

Hi Subashbabu,

       

The I/O standard for QDRII+ :  HSTL-I inputs and variable drive HSTL-I output buffers.

   

It supports both 1.5 V and 1.8 V I/O supply

       

Thanks

[Anonymous]

 Hi 

   

   As you said the input IOstandrad is HSTL_I and output IOStandard is HSTL_DCI_I(Variable) .

   

As the given formula for the resistance the 

   

input  R = RQ/3.33 , i have taken the RQ = 250 ohms then 

   

Rinput =75 ohms

   

output R = RQ/5 then

   

Routput = 50 ohms

   

The output resistance of the memory  or the input resistance of the FPGA internal. 

   

As given reference schematic design in WEB the output does not have the output resistance

[Anonymous]

QDR II+ support HSTL-I i/o standard. For outputs, the impedance can be varied.

[Anonymous]

RQ/3.3 determines the on-die termination resistance on the input pins. You can select ODT low range and have this value almost equal to 50 ohms.

[Anonymous]

 Hi 

   

  For the output resistance is RQ/5. It is correct. The output resistance are in build to the memory . In the knowledge article the output does not have any output resistance in that schematic the input is having the resistance.

   

Thanking you

[Anonymous]

 Reference Schematic Design Recommendation for QDR-DDR II/II+/Xtreme SRAMs - KBA84386

[PriteshM_61 · Accepted solution]

Hi Subashbabu,

       

Please find the attached file with this interaction. We have updated the article and will publish it on web as early as possible. We can also have a quick call to discuss the same. Please send me your contact details on prit@cypress.com

       

Thanks