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SRAM

user_4632561
New Contributor

Hi,

We found an Application Note (AN88889) on CYPRESS website, which describes architecture of the CYPRESS 65 nm SRAM technology with ECC embedded, like the two references CY7C1041G30 and CY7C1041GE30. So we wonder if the architecture of the CY7C1041GN30 is partially the same as the others references like CY7C1041G30 and CY7C1041GE30.

  • Is there Bit Interleaving in the CY7C1041GN30 architecture?
  • Is there a 32 bits buffer (partial Hamming code architecture) for the Read and Write operations in the CY7C1041GN30 architecture?
  • Does it include also an embedded ECC ?

If yes, it could explain the results of our radiation tests. Could you give us some information about this?

Thanks for your Interest on our request.

François DESNOYERS

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PradiptaB_11
Moderator
Moderator

Hi,

Bit Interleaving architecture is used in all 65 nm SRAMs. CY7C1041GN30 also makes use of this architecture.

Internally, the SRAM uses a buffer for read and write operations. CY7C1041GN30 also uses a buffer. There is no hamming code implementation/ or Embedded ECC on CY7C1041GN30.

Regards,

Pradipta.

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