Anonymous
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Sep 21, 2016
01:43 AM
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Sep 21, 2016
01:43 AM
2 Replies
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Anonymous
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Nov 23, 2016
01:52 AM
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Nov 23, 2016
01:52 AM
Apr 19, 2017
04:34 AM
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Apr 19, 2017
04:34 AM
Hi Krishna,
Thanks for reference schematic. Signals CQ/CQ# from 2_DDR II+ are not connected. I can calculate the worst-case data valid window (DVW) when reading from 1_DDR II+ :
DVW = tCQHCQH - tCQHQV + tCQHQX.
How can I calculate the worst-case data valid window, when reading from 2_DDR II+, if I use echo clocks from 1_DDR II+ to capture data?