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SRAM

YangZhong
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Hi ,in my board, i use Xilinx IP to Access  CY7C2665KV18.

when in write process, BWS signal looks strange, maybe with ODT Problem.

YangZhong_0-1654753141808.jpeg

The yellow signal is WPS signal

The green signal is BWS signal

When WPS is high, BWS signal can toggle around 750mV

But when WPS is Low, in write process, BWS signal can't higher than 750mV

 

YangZhong_1-1654753358672.jpeg

 

YangZhong_2-1654753377132.jpeg

YangZhong_4-1654753412668.jpeg

 

 

 

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ritwicksharma
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Hi @YangZhong,

 

Could you please share the schematic with us?

 

Thanks,

Ritwick

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YangZhong
Level 1
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Hi Ritwick

Sram side schematic with below, and FPGA Side BWS signal direct connect to SRAM without Pull up/down

YangZhong_0-1654779101480.png

Thanks 

Yangzhong

 

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ritwicksharma
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Hi @YangZhong,

 

> Could you please let me know why there is so much variation in WPS and BWS signals? Is the power supply stable?

 

> Please pull up the lines to VDDQ, not Vtt.

ritwicksharma_0-1655113398151.png

 

> Please connect decoupling capacitors to the VDD and VDDQ.

ritwicksharma_1-1655113549401.png

 

> As low is provided to the ODT pin, ODT termination would be RQ/3.33 ~ 75 ohms. Is your trace impedance also ~75 ohms. For more details on proper termination, please refer to our App note- AN4065

 

Thanks,

Ritwick

 

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YangZhong
Level 1
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Hi Ritwick

> Could you please let me know why there is so much variation in WPS and BWS signals? Is the power supply stable?

Power is stable. Variation come from GND noise.

 

> Please pull up the lines to VDDQ, not Vtt.

Why? pull up to Vtt is right.

 

> Please connect decoupling capacitors to the VDD and VDDQ.

There are many decoupling capacitors to the VDD and VDDQ not show in the pic

 

> As low is provided to the ODT pin, ODT termination would be RQ/3.33 ~ 75 ohms. Is your trace impedance also ~75 ohms. For more details on proper termination, please refer to our App note- AN4065

I removed the R6 when testing.

 

Thanks 

Yangzhong

 

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YangZhong
Level 1
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Hi Ritwick

Address pin pull up to Vtt is right

YangZhong_0-1655444625510.png

Thanks 

Yangzhong

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ritwicksharma
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Hi @YangZhong,

 

That Vtt pull-up is for active pull-up termination. Please note the termination resistor (R) value must be equal to the characteristic impedance of the trace. Is your characteristic impedance of the trace 39.2 Ω?

Could you please probe the pins of Xilinx connected to WPS and BWS pins and share the scope shots with us? You had sent the scope shots for WPS and BWS, so now I want to check the waveforms of the source side.


Thanks,
Ritwick

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YangZhong
Level 1
5 replies posted First reply posted First question asked
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Hi Ritwick

>That Vtt pull-up is for active pull-up termination. Please note the termination resistor (R) value must be equal to the characteristic impedance of the trace. Is your characteristic impedance of the trace 39.2 Ω?

The trace characteristic impedance is 40ohm.

>Could you please probe the pins of Xilinx connected to WPS and BWS pins and share the scope shots with us? You had sent the scope shots for WPS and BWS, so now I want to check the waveforms of the source side.

Sorry i can't probe the pins of FPGA at the source side.

Could you help to see the waveforms again

The yellow signal is WPS signal

The green signal is BWS signal

YangZhong_0-1655542451325.jpeg

Why BWS signal can toggle well in read process?

If the BWS signal always toggle fail, there must be some problem.

But actually, BWS signal some times toggle well, some  toggle fail.

 

Thanks

 

 

 

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YangZhong
Level 1
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Hi Ritwick

Does the ODT for BWS inside the SRAM always enabled?

The Pu or PD value decided by RZQ?

YangZhong_1-1655544897506.png

 

Thanks

 

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ritwicksharma
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Hi @YangZhong 

 

> Why BWS signal can toggle well in the read process? If the BWS signal always toggle fail, there must be some problem. But actually, BWS signal sometimes toggle well, some toggle fails.

 - Why would BWS toggle during the read process?

BWS stands for Byte write select and is used to select which byte is written into the device during the current portion of the write operations. Could you please elaborate on toggle well and toggle fail? How do you identify toggle fail and well?

BWS is just a digital input signal. You either have to provide 1 or 0 during a write operation.

 

> Also, could you please let me know the problem? Is there any problem related to read/write?

 

> Are there decoupling capacitors present on Vtt? Please refer to the section- Decoupling Capacitor Recommendations for Power Supply Pins of  AN4065

 

> Does the ODT for BWS inside the SRAM always enabled?

- Yes.

 

> The Pu or PD value decided by RZQ?

- Yes.

 

Thanks,

Ritwick

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YangZhong
Level 1
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Hi Ritwick

Thanks for your reply.

 

>Why would BWS toggle during the read process?

In my testing, when BWS keeps Low, the Read/write function is OK.

But when i use the Byte write select function, some unwanted data still written into sram.

Then I create the test pattern -- BWS signal toggle in write process, and check the signal with oscilloscope, then find the BWS signal can't higher than 750mv.

So i create another test pattern, BWS signal always toggle, then found BWS seems toggle well in read process and fail in write process. 

It's the whole story.

 

 > Are there decoupling capacitors present on Vtt? Please refer to the section- Decoupling Capacitor Recommendations for Power Supply Pins of  AN4065

YangZhong_0-1655878322623.png

Besides these capacitors, there are another 2x10uf+1x47uf.

 

> Does the ODT for BWS inside the SRAM always enabled?

> Yes.

Because the ODT for BWS always enabled and BWS is just a digital input signal.

When BWS always toggle, I think the waveform should be same always.

But now it's clearly different.

 

Thanks,

Yangzhong

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ritwicksharma
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Hi @YangZhong,

 

 > Could you please let me know what your "Byte write select function" is doing? Is it creating the test patterns?

> "BWS seems to toggle well in read process and fail in write process." Again, how are you identifying if the toggle is well or not?

> Also, your trace characteristic impedance is 40 Ω, and as per your configuration, the ODT resistance is 150 Ω (RQ/1.66) which is not a matched design. You should change the RQ to 175 Ω and make the ODT pin low for proper matching.

ritwicksharma_0-1655896318056.png

 

Thanks,

Ritwick

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YangZhong
Level 1
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Hi Ritwick

 > Could you please let me know what your "Byte write select function" is doing? Is it creating the test patterns?

In case of modify part date bytes in some address, and other data bytes remain unchanged.

 

> "BWS seems to toggle well in read process and fail in write process." Again, how are you identifying if the toggle is well or not?

My definition of toggle well is just the waveform, according to HSTL IO Standard, Logic High = 750mV + 100mV min, and Logic Low = 750mV - 100mV min

 

> Also, your trace characteristic impedance is 40 Ω, and as per your configuration, the ODT resistance is 150 Ω (RQ/1.66) which is not a matched design. You should change the RQ to 175 Ω and make the ODT pin low for proper matching.

Thanks, I well do the experiment.

 

Thanks,

Ritwick

 

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YangZhong
Level 1
5 replies posted First reply posted First question asked
Level 1

Hi Ritwick

> Also, your trace characteristic impedance is 40 Ω, and as per your configuration, the ODT resistance is 150 Ω (RQ/1.66) which is not a matched design. You should change the RQ to 175 Ω and make the ODT pin low for proper matching.

>Thanks, I well do the experiment.

I Changed RZQ to 200Ω, and noting changed.

 

Thanks

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ritwicksharma
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Hi @YangZhong,

> I could not understand what your Byte Write select function does. What did you mean by "In case of modify part date bytes in some address, and other data bytes remain unchanged."?


> There is no need to toggle BWS lines during the read process. Let it be high. Also, as BWS is an input signal, you have to ensure that it is meeting the Vih and Vil parameters for correct operation.


ritwicksharma_0-1655987373857.png


> I Changed RZQ to 200Ω, and noting changed.
- Are you tying the ODT pin low? Also, try changing RQ to 175 Ω along with tying the ODT pin to low for proper matching.

> Your main issue is unwanted writes during toggling BWS signals, correct?

Thanks,
Ritwick

 

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