CY7C1168KV18 bidirectional bus (DQn...) termination

[ErezN]

Hi,

CY7C1168KV18 contain bidirectional data bus DQ.

The DQ port has build in serial termination but lack of active pull-up termination (for receiving mode).

The FPGA I'm using contain both termination (serial and  active pull-up termination).

The question is should I add external pull-up termination to the DQ bus?

(In AN4065 design example DQ doesn't have active pull-up termination)

[PradiptaB_11]

Hi @ErezN ,

For your application the device CY7C1168KV18 is a non ODT part and you can use the reference schematic for non ODT device. For this you will need to add the external pull ups on the DQ lines.

Thanks,

Pradipta.

[ErezN]

Hi,

Thanks.

Making sure I understand correctly, the DQx pins will have two pullups termination, one on the FGA side (the FPGA has internal termination) and one on the ram side (added externally)?

(In AN4065 design example for none ODT SRAM, DQ doesn't have external active pull-up termination.)

Best regards,

Erez

[PradiptaB_11]

Hi @ErezN ,

The Data output (Q[x:0]) and Echo Clock (CQ/CQ#) signals drive the FPGA/ASIC without termination,
considering the inputs of the FPGA/ASIC that supports ODT. I missed this fact in your earlier response and hence asked you to go for a termination on DQ lines. As your FPGA already has internal termination available you do not need any external resistance for termination.

Thanks,

Pradipta.

[ErezN]

Hi Pradipta,

Thanks again for you prompt response.

If I understand correctly when DQx pins serve as output (from RAM to FPGA, read operation) the signal will have serial termination at the source (SRAM) and parallel termination at the destination (FPGA).

At the opposite direction (from FPGA to RAM, write operation) the signal will have only serial termination at the source (FPGA) but not parallel termination at the destination (SRAM), might cause  reflection.

Due the to above do you recommend any restriction on DQ length or.....?

Best regards,

Erez

[PradiptaB_11 · Accepted solution]

Hi @ErezN ,

For all our design guidelines please refer to the application note as below.

When the DQx pins serve as output the signal will have termination only at the FPGA end. There is no termination at the source end. You will get impedance matching with this setup.

During write operation the data input lines have ODT enabled. You will not have reflection issues. You can refer to various termination settings in our app note as well for more information on this.

https://www.infineon.com/dgdl/Infineon-AN4065_QDR-II_QDR-II%2B_DDR-II_and_DDR-II%2B_Design_Guide-App...

https://www.infineon.com/dgdl/Infineon-AN42468_On-Die_Termination_for_QDR(R)_II+_DDR_II+_SRAMs-Appli...

Thanks,

Pradipta.