Good morning, I am currently working on the development of a product which includes CY62157EV30LL-45ZXA SRAM.
We are using the device in 8-bit data mode, using address pins A0-A19, with BHE and BLE tied high, and BYTE tied low.
In many areas of the datasheet, it is specified that '29. During this period, the I/Os are in output state. Do not apply input signals.'
We understand this that if the I/Os are in an output state, and we drive a voltage into these pins at this time - it is possible that we may physically damage the memory. We are not comfortable shipping a product that could be damaged by firmware - validated firmware or not.
Are we understanding this correctly? And in such a case, would Infineon recommend the use of series resistors on the data lines to stay within the 20mA 'output current into outputs (LOW)' specification, within the maximum ratings section of the datasheet?
Many thanks in advance
During that time, the WE# line is high. So, the data won't be written into the memory, just the read data won't be reliable. However, applying input signals does not make sense during the read operation (when I/Os are in output state).
Hi Ritwick, thanks for your response.
I understand that it would not make sense to apply input signals in this state, but my question is what happens if this does occur? Will the SRAM be damaged?
The datasheet does not have an image describing the I/O pin structure, so we are not sure.
We don't have any recommended resistor value as that "operation" is not expected for the desired functioning. However, you can measure the current during the "operation" (mentioned by you), and if it exceeds 20 mA, please use a current limiting resistor accordingly.
Thanks, we will setup a bench test to try this.
Do you know if the SRAM's input circuitry will even sink/source more than 20mA, or is the 20mA a max rating for current injection above the supply rail voltage?
20 mA is the maximum rating, and exceeding the maximum rating spec may shorten the useful life of the device, and we don't guarantee anything above the maximum ratings.
May I know the duration for which you would be doing that "operation"(applying input signals during the read operation)?
Thanks for your response. I understand that 20mA is the absolute maximum rating; this is the reason for our concern.
Apologies, I don't think I've explained our concern particularly well. We do not intend to perform this "operation", but rather we are concerned about what happens if we do, by mistake.
For example; during firmware development, if one of the address lines is mistakenly driven high, for an indefinite duration, will this damage the SRAM IO pin/port?
This condition shouldn't occur, but equally if it did - it could be 10s of nsec, or it could be several minutes.
If one of the address lines is mistakenly driven high, it is a different issue. In this case, you won't be applying input signals on the I/O lines, as there are separate input pins for address.
And if mistakenly one of the address lines is driven high, then there would be data reliability issues. You have to meet the timing specs as mentioned in the datasheet. You have to keep the address lines stable for at least tRC (45 ns) duration for desired operations.
Sorry Ritwick, there was a mistake in my previous post. I meant to say data, not address.
I meant to say:
For example; during firmware development, if one of the
address data lines is mistakenly driven high, for an indefinite duration, will this damage the SRAM IO pin/port?