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PSoC 6 SysClk

PSoC 6 SysClk

Anonymous
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PSoC 6 SysClk

Hello,

Thought I'd give an introduction on SysClk in PSoC 6 MCUs. PSoC 6 has an Frequency Locked Loop (FLL) and a Phase Locked Loop (PLL). Both can be used to create High Frequency system clock. For example you can use the FLL to create a clock to run the CM4 and CM0+ cores, while the PLL can be used to clock the audio subsystem. The FLL can achieve an output frequency of up to 100 MHz, while the PLL can reach the device maximum of 150 MHz. The input of the PLL and FLL can be the on board 8 MHz IMO, and external crystal oscillator (ECO), among several other sources.

The PSoC 6 device also contains several programmable clock dividers that can be used to clock peripherals such as Serial Communication Blocks (SCBs), Timer/Counter/.PWMs (TCPWMs), and Universal Digital Blocks (UDBs). There are 8 x 8-bit dividers, 16 x 16-bit dividers, 4 x 16-bit fractional dividers with 5 fractional bits, and 1 x 24-bit divider with 5 fractional bits.

Feel free to ask questions and leave comments!

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cadi_1014291
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Hi,

What is the highest frequency the UDBs can run at?

MeenakshiR_71
Employee
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Employee

Maximum frequency of operation for UDBs is 100 MHz.

CM0+, SCBs, TCPWMs and most of the peripherals also have the same maximum operating frequency.

CM4 can run upto 150 MHz.

cadi_1014291
Level 6
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Level 6

Thanks for the reply .

I got a off-topic question, given that the UDBs run at the same frequency as the CM0+ that made me wonder if the UDB bank is located into the CM0+ part of the die?

and Are UDBs reachable from both cores?

Thanks in advance

MeenakshiR_71
Employee
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Employee

I can understand the curiosity. To answer the question, I would like to add another note from the design, both CM4 and CM0+ share the same 32-bit MMIO address space. Including UDBs, all other peripherals are part of this address space which both the cores can access. We do have multiple arbiters in place for regulating simultaneous access by multiple masters (CPUs, DMAs etc). You can refer to our Dual-Core CPU design app note draft for details.

cadi_1014291
Level 6
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Level 6

Hi msur,

Thanks for the clarification, i forgot that both cores share the same MMIO address space .

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