PSoC 6 Continuous Time Block mini (CTBm)

[Anonymous]

Hello!

Thought I'd give an update on the Continuous Time Block mini (CTBm) resource in the PSoC 6 architecture.

The Continuous Time Block mini (CTBm) provides the core flexibility of the analog sub-system in PSoC 6. The CTBm interconnects with the analog sub-system supporting input and output connections to GPIO pins, CTDAC voltage source, and SAR ADC inputs. In the initial PSoC 6 release, the PSoC 63 Connectivity line, two configurable OpAmps with programmable routing are included that provide the following features:

• Two OpAmps with programmable power, bandwidth, and output drive strength to optimize power and performance for your design. Can be optionally enabled in DeepSleep low power mode.
• OpAmps can be used individually or together to make higher level functions like a differential amplifier.
• Each OpAmp can be configured as a comparator with optional 10 mV hysteresis and generate interrupts on both rising and falling edges.
• OpAmps can be configured as unity gain buffers using internal routing or as gain amplifiers with user supplied external gain resistors.

Feel free to leave comments and ask questions, we appreciate the feedback!

[Anonymous]

I've got the CY8KIT-062.  I'm trying to program the CTBm to generate 2V.  Do you have any examples for programming the CTBm?

As I understand using the CTDAC is the only way to get a 2V output on the PSoC6.

• The concern I have is that I cannot use the CTDAC directly to generate 2V. The reason is that the VDDA supplying the CTDAC will be dropping as the battery voltage drops. Therefore, I cannot expect a consistent 2V using the CTDAC directly.
• Therefore, I am planning to use P9.3 and the CTBm OA1 as a 2V output voltage rail for U301 buffer/level shifter using the CTDAC with OA1 to be a PGA and using VREF as the OA1 reference. The goal would be generating a 2V output regardless of the VDDA/battery voltage. I have yet to demonstrate this will work. Could you confirm with Cypress if this is feasible

PSoC6 Architecture TRM 002-18176, section 35 page 425 for CTDAC

35.3.1.4 Other Configurations

The CTDAC with the Opamp1 can be used to implement a PGA (see Figure 35-10). In this configuration, the COR switch feeds back the Opamp1 output through the R-2R divider. The CTDAC_VAL register controls the gain of the amplifier. The gain is given by (1+4095/CTDAC_VAL)

[Anonymous]

I received a response from Cypress app engineer, Meenakshi Sundaram R.  He was very helpful.  Here's what he said:

Few things to note before you use the example -

1. The formula in the TRM is wrong, it will be updated in the next rev. The correct formula is 4095/CTDAC_VAL

2. In order to use P9.3 in the kit, you will have to remove a resistor. By default, P9.3 is used for trace data in the kit. I am not sure of the REV of the board you have (REV number is available at bottom side of the board, above J4). In my board (REV02), I had to remove R105 and populate 0 ohm R106 for routing P9.3 to the header. if you have schematic, you can refer that as well for the resistor number (search for P9_3).

I did a quick test and was able to get 2 V at P9.3. The code I used is below. I will try to get you PDL '.c'/'.h' files for CTBm and CTDAC. For quick testing, you can use the below code (nothing required in TopDesign/dwr):

/* Configure PASS trims - ** silicon does not load the trim data for PASS

  If not loaded, the references will be slightly off

  Note that these are default/design trims and can still result in slightly incorrect reference values */

  PASS->IZTAT_TRIM0 = 0x20;

  PASS->IZTAT_TRIM1 = 0x9;

  PASS->IPTAT_TRIM0 = 0x88;

  PASS->ICTAT_TRIM0 = 0x9;

  PASS->VREF_TRIM0 = 0x20;

  PASS->VREF_TRIM1 = 0x15;

  PASS->VREF_TRIM2 = 0xA2;

  CTBM0->OA0_COMP_TRIM = 0x03;

  CTBM0->OA1_COMP_TRIM = 0x03;

  /* Configures AREF to use PASS reference (1.2 V) instead of SRSS (0.8 V), enables it in DeepSleep mode */

  PASS_AREF->AREF_CTRL = PASS_AREF_AREF_CTRL_ENABLED_Msk | PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk | 0x30110000;

  /* Configure CTDAC */

  CTDAC0->CTDAC_CTRL = CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk | CTDAC_CTDAC_CTRL_OUT_EN_Msk;

  CTDAC0->CTDAC_VAL = 2457; //Gain = 4095/CTDAC_VAL

  /* Configure CTBM OA1 */

  CTBM0->CTB_CTRL = CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk;

  CTBM0->OA_RES1_CTRL = 0x00000003 | CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk | CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk; // 3 - High power mode, 2 - Medium and 1 - Low

  /* Configure all the switches */

  CTBM0->OA1_SW = CTBM_OA1_SW_OA1P_A73_Msk | CTBM_OA1_SW_OA1O_D82_Msk; 

  CTBM0->CTD_SW = CTBM_CTD_SW_CTDD_CRD_Msk | CTBM_CTD_SW_CTDS_COR_Msk;

  /* Enable CTDAC and CTBM */

  CTDAC0->CTDAC_CTRL |= CTDAC_CTDAC_CTRL_ENABLED_Msk;

  CTBM0->CTB_CTRL |= CTBM_CTB_CTRL_ENABLED_Msk;

[Anonymous]

Forgot to mentioned, this worked for me.  I was able to generate a stable 2V on P9.3 using the CTBM0